Oziphantom wrote: ↑
Mon Mar 02, 2020 1:07 am
As you had issues with the address pins, I would double check the data pins as well. You can open the ROM in a hex editor and see what values it should read at those locations and make sure your logs match.
I crossreferenced the ROM when I initially had this problem because that is what I thought was the issue. It doesn't match, so I am on the same page as you. I think the issue is in my ROM wiring on the board.
nocash wrote: ↑
Mon Mar 02, 2020 3:23 am
/RD must be getting low when reading the reset vector, if it isn't: You have used the wrong pin, or it's shortcut to VCC. Or, if the logic analyzer is synced to the SNES cpu clock, then you might sample the /RD signal at the wrong time, and thus won't see the periods when it gets low.
Does address 3FFCh still occur? That should be FFFCh. And don't forget that LoROM doesn't use A15, so it would be at offset 7FFCh in the memory chip.
I thought of that last night before bed. I was only using state analyzer because I was thinking the SNES was slow compared to my LA. I have the HP 1652B which has a speed of 250MHz, but since it only triggers on clock edges, I could still be missing the signal. I'll set it up in timing machine mode tonight and see if I can see the RD signal at all. I will double check the pin I have it connected to, but I looked them all over yesterday when I first had the issue.
$3FFFC doesn't happen any more (or I should say never happened), that was just a problem with my analyzer connections. I am using mode 21 on these boards so I still have A15 used.
I was thinking to try and tie the 27C322 /CS and /E to gnd and just use the mux OE to gate the ROM onto the data bus and see if that works. Right now I have both 74257s and the 27322 /OE on the same signal (1Y3 from 74139). I am thinking that reading from the ROM is the main issue, not that it's reading the wrong data.