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PostPosted: Wed Oct 13, 2010 12:42 pm 
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Joined: Wed May 19, 2010 6:12 pm
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"CHR RAM accessed how fast? If you've ever played Videomation, you'll probably remember how slow its flood fill is."

I've been thinking about 21 Mhz, but I'm not sure what speed to allow the 63C09 to access SRAM, because it has to be accessed by the FPGA too.

I'll do some math. A 21 Mhz has 1365 cycles per line. If I let the 63C09 access the SRAM at 5 Mhz which is 341 cycles per line, I will have 1024 left over cycles for the FPGA to access.
1024 - 336 color palette accesses = 688 cycles
688 - 160 y-coordinate sprite entries = 528 cycles
528 / 6 accesses per sprite (x-coordinate, attributes, 4 patterns) = 88 sprites per line.
88 sprites / 22 sprites per layer = 4 layers of parallax before flickering

160 sprites with 88 sprites per line is pretty good.

I advise be careful when using the offset-per-tile joining bit. If the host sprite isn't on the scanline, the joined sprite will use the last rendered sprite's x-coordinate as the host sprite instead. Use a blank tile on top and bottom of the sprite strips to avoid visible glitches when using tile-per-offset joining.

The only thing that I don't know yet is what should I do about 8x8 text like score boards?

EDIT: I fixed some broken math.


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