Sure I can tell ya. Right now I am using a cyclone 3 25K model, same size chip (240 pins) as the previous model, but 2x more gate-age.jwdonal wrote: That's really cool. I'm not even close to where you are. Is this all still fitting in the Cyclone I with ~12K LEs? Or have you moved to a larger device? It's hard for me to compare Altera devices resource wise to Xilinx (which is what I'm using) since Altera vs. Xilinx resource terminology is very different. It looks like on your new board the Cyclone chip is a bit bigger this time around - did you move up to a Cyclone II instead? Also, (and yes I realize this may be considered NDA/proprietary/secret so I don't actually expect an answer to this, lol) what current resource utilization are you at within the cyclone with the entire CPU+PPU+APU+mappers+etc? 25%, 50%, 75%, 90%?
So from you've said it appears you've moved away from the original PIC microcontroller and replaced it with this Vinculum 2 instead. PIC is certainly very popular whereas I've never heard of the Vinculum before. PIC also has good IDE tools and lots of freely availble IP. Why did you switch away from the PIC? Was there something that you just really didn't like about it?
Also, I sent you a PM regarding a very specific CPU design question. I didn't post it here because it doesn't relate at all to this topic and don't want to get things off-track. Mind taking a peak?
Pz!
Jonathon
It is using 65% of the device for everything, and I expect it to hit 70% when I finish the vinculum interface stuff to do system control.
It does not fit on the old FPGA any more, but it could easily be trimmed to fit if needed, though I have finished with that old hardware now and won't use it again probably.
I selected altera, because xilinx's programming environment is a huge steaming pile of poo. Buggier than a swamp in june, in #nesdev I watched people struggle with it; compiles that work but then the device doesn't, unless they downgrade the compiler.
the entire design is all verilog now, with a single top level schematic just linking 6 or so verilog top modules together (CPU, PPU, mappers, audio, video, controllers, SDRAM). All of the hardware-specific pieces are cordoned off in a single verilog "Technology" file as I called it, mainly the blockrams. This was in case the design needs to be ported, it should be possible to just replace this 1 file and it can work on another vendor's parts.
As memblers said, I changed from PIC to vinculum because I wanted 2 USB ports on it for controllers. So far I have had problems just getting the damn thing to compile and work but I got all that solved and the chip is happily lighting the segments of the LED display up in a cylon-like pattern. At this point I am going to write all the basic hardware interface doohickeys and go from there.
This vinculum chip is fairly cheap, too.