Discrete Logic Mapper Toolbox

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tepples
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Re: Discrete Logic Mapper Toolbox

Post by tepples » Thu Sep 06, 2012 6:37 pm

lidnariq wrote:2 ICs:
Inverter + RAM
→ Map 8KB RAM into PPU $0xxx and $2xxx for 4KB CHR-RAM slice and 4-screen mirroring, inverter makes NOT A12 to decode 4KB ROM (or 4KB window) in $1xxx
Wow. Clever. That allows a separate background bank at $1000 for each locale type while still allowing arbitrary combination of sprites ($0000).

80sFREAK
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Re: Discrete Logic Mapper Toolbox

Post by 80sFREAK » Fri Sep 07, 2012 5:05 pm

subscribed

IMO playing with discrete logic is like playing chess, while PAL/CPLD is simplier and faster to design, but not that much fun.

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Re: Discrete Logic Mapper Toolbox

Post by lidnariq » Fri Sep 07, 2012 5:49 pm

Some more ideas:

1or 2 ICs (1 is sort of cheating):
Tristatable dual 4-input multiplexer (74'253) in lieu of CHR ROM, plus 8 ≈1kΩ resistors (or a 74244):
→ Game Genie style low-resolution graphics, where each 4-by-4 pixel zone is individually controllable and can have any color D3…D0←SEL(A3…A2,A11…A8) and D7…D4←SEL(A3…A2,A7…A4)

3 ICs:
Tristatable latch (74'373), logic (½(7421 or 7420) + (½ 74139))
→ Use two bits of tile number for attribute instead of attribute tables. (Decode /NAMETABLE or /ATTRIBUTETABLE, and latches D7,D6 from the data bus on the former (as well as enabling the internal RAM) and enables the latch output on the latter)

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Re: Discrete Logic Mapper Toolbox

Post by zzo38 » Wed Sep 12, 2012 10:47 pm

.
Last edited by zzo38 on Mon Jun 10, 2013 9:05 pm, edited 1 time in total.
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Re: Discrete Logic Mapper Toolbox

Post by lidnariq » Wed Sep 12, 2012 11:20 pm

The reset circuit as I described was used in Caltron 6-in-1. A variant that used CPU A0 instead of M2 was used in Maxi 15.

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Re: Discrete Logic Mapper Toolbox

Post by lidnariq » Sun Mar 10, 2013 1:40 am

Here's another one:

1 or 2 ICs (1 is sort of cheating), for use with CHRless mapper 218:
74'153 or 74'157, plus 8 ≈10kΩ resistors (or a 74244):
→ Allow selective disabling of 1kB NT RAM so-as-to split bitplanes. CIRAM/SEL ← SEL(A3,A10,A11), SEL/E ← A13, D0…D7 ← A12 through resistors or buffer
The middle third is necessary to make sure that the nametable doesn't randomly lose tiles; the first means that the first 1kiB is normal, while the 2nd and 3rd kiBs will be only the 1s or 2s bitplanes. The last third allows switching banks ($0000 vs $1000) to select whether the result slicing is 0-vs-2 and 0-vs-1 or 1-vs-3 and 2-vs-3. (The resistors are still desirable regardless; otherwise for these fetches the PPU's input will be open bus)

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Re: Discrete Logic Mapper Toolbox

Post by lidnariq » Thu May 02, 2013 8:57 pm

While talking about the UxROM-512 thread, I thought of another one:

2 ICs: UNROM without bus conflicts:
use 74'02 instead of 74'32
Reverse 16KiB slices before burning. Use last NOR gate to invert RnW to produce /RD and connect that to the ROM's /OE pin.
Correspondingly, the maximum size is now only 128KiB.

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Re: Discrete Logic Mapper Toolbox

Post by infiniteneslives » Thu May 02, 2013 9:07 pm

This caught me off guard the other day. It's actually much simpler than that. Just use flash for PRG-ROM and connect /WE to PRG R/W. It won't output unless /WE is high, bus conflicts eliminated...
If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

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Re: Discrete Logic Mapper Toolbox

Post by lidnariq » Thu May 02, 2013 10:06 pm

That behavior depends on the specific memory you're using, though... e.g. the 28xxx and 29xxx series seem to in general have /OE entirely override /WE; the non-flash 27xxx series don't have a /WE strobe at all, and the 39xxx and 49xxx ones I've found don't say.

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Re: Discrete Logic Mapper Toolbox

Post by infiniteneslives » Thu May 02, 2013 11:12 pm

There are lots of specifics. Nothings to say you can't take benefit of a feature that exists if you ensure it's there.

I was in one of those situations where I forgot to do something and it worked. The next day I realized I forgot to prevent the conflicts and couldn't figure out why it actually did work. Then it dawned on me how easy it was to prevent bus conflicts when using flash (assuming you've verified it works as you need it to.)
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Re: Discrete Logic Mapper Toolbox

Post by zzo38 » Mon Jun 10, 2013 9:04 pm

Could you connect CHR A13 to a clock input of a flip-flop which then output to CIRAM A10 in order to make the attribute areas smaller? (This might make it more difficult to load the data into the nametables, though)

Could you somehow make special effects with the audio if there is something to switch on/off the audio by the CHR address or CHR data lines?

Maybe you can change the attribute areas if you combine the CHR A13 with one of the other address lines on a latch, in order to affect CIRAM A10, so that when it reads the pattern table for a tile, then which of two internal name tables is used for the next tile is selected using that?

Perhaps you can have nametable mirroring controlled by which mirrors of the PPU registers are being used?

Possibly with a programmable counter you could add an extra square channel of audio?

Maybe you can connect CHR A11 (or CHR A10, depending on what you want to do) and CHR A13 to the IRQ, in order to make a scanline IRQ by setting the scroll position?

You could also perhaps use the IRQ to communicate the cartridge with a device connected to the Famicom expansion port?

Maybe even to make a kind of bank switching without any IC by putting a wire in the Famicom expansion port connecting OUT2 (or OUT1) with IRQ?

There may be many more possibilities, too.
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Re: Discrete Logic Mapper Toolbox

Post by zzo38 » Tue Jun 11, 2013 1:07 pm

You could possibly connect the CHR A10 or CHR A11 lines of the cartridge to a latch which is wired to one of the address lines on the CHR ROM, in order to make different tiles for a split screen.

Make 8x8 attribute areas by a logic to detect attribute table address; the name table address is then stored in a latch, which is connected to a CHR RAM in the cartridge, and is activated (and the CIRAM disabled) when the attribute table is being accessed, instead of using the actual attribute table addresses.

If you have some kind of RAM with one read-only bus and one write-only bus (I don't know if any such thing exist), then with a little bit of decoding logic you might be able to make it so that writes to PRG addresses $1xxx are copied into the CHR RAM (although then you can't write CHR RAM through the PPU).

Would any of these work? Would anything from my previous message work?
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infiniteneslives
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Re: Discrete Logic Mapper Toolbox

Post by infiniteneslives » Tue Jun 11, 2013 8:29 pm

It's pretty hard to even being to grasp what exactly you mean by some of these ideas. They are pretty vague on how exactly you imagine to implement them since how many of the parts are imaginary at this point... So there isn't much ability to begin to analyze what will work and what won't. In general I'd say most of the things you're trying to do are with an underpowered piece of hardware, but I really don't know what half of these ideas are.

Q: Could you possibly somehow, connect two things and have a random PPU register to maybe control something?
A: Sure, connect an FPGA to every pin on the NES/FC mobo and you can do anything...
If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

zzo38
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Re: Discrete Logic Mapper Toolbox

Post by zzo38 » Wed Jun 12, 2013 12:26 pm

I am sorry for being difficult. I don't have time now but when I do, I can write it more specifically, which kind of logic chips to use and so on, possibly to make the schematics too, to explain more precisely what I meant.
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lidnariq
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Re: Discrete Logic Mapper Toolbox

Post by lidnariq » Thu Jun 13, 2013 12:19 pm

zzo38 wrote:Could you connect CHR A13 to a clock input of a flip-flop which then output to CIRAM A10 in order to make the attribute areas smaller? (This might make it more difficult to load the data into the nametables, though)
You could, but I'm not certain it would have a desirable effect. It would either give you 8x16 attribute zones, or it would alternate every scanline and you'd end up with checkerboard attributes. It depends on whether there's an even or odd number of PPU A13 transitions over the course of a scanline. It would be very fiddly and require very careful attention to scrolling. Furthermore, both nametables use the same combined attribute table, although one's the opposite of the other.
Could you somehow make special effects with the audio if there is something to switch on/off the audio by the CHR address or CHR data lines?
No more so than the experiment done of hooking the video RCA jack directly to an audio input.
Maybe you can change the attribute areas if you combine the CHR A13 with one of the other address lines on a latch, in order to affect CIRAM A10, so that when it reads the pattern table for a tile, then which of two internal name tables is used for the next tile is selected using that?
I guess this lets you get programmatic non-square split screens? I guess that lets you do interesting wipes. I don't see a way to do it in fewer than 3 ICs, though.
Perhaps you can have nametable mirroring controlled by which mirrors of the PPU registers are being used?
Not any more convenient than established discrete logic mirroring control. The only difference is decoding $2000-$3fff and latching on read/writes to it instead of writes to $8000-$ffff.
Possibly with a programmable counter you could add an extra square channel of audio?
You could add an 8254 to a cartridge, which is three independent timers. They could most easily be used for interrupts or sound. But the 8254 is quite expensive, and at that point you may as well use a tiny microcontroller.
Maybe you can connect CHR A11 (or CHR A10, depending on what you want to do) and CHR A13 to the IRQ, in order to make a scanline IRQ by setting the scroll position?
If you used something like a 74'03, you could have the /IRQ line asserted for a substantial portion of the screen.
You could also perhaps use the IRQ to communicate the cartridge with a device connected to the Famicom expansion port?
I'm pretty certain that's the point. To be able to tell the program "I've got data for you".
Maybe even to make a kind of bank switching without any IC by putting a wire in the Famicom expansion port connecting OUT2 (or OUT1) with IRQ?
Since /IRQ only goes to the CPU, and OUT2 only comes from the CPU, that's not useful.

On the other hand, on a toaster NES, one could connect OUT2 to the expansion port, allowing mapper 99 games without any additional hardware.
zzo38 wrote:You could possibly connect the CHR A10 or CHR A11 lines of the cartridge to a latch which is wired to one of the address lines on the CHR ROM, in order to make different tiles for a split screen.
Like mapper 96?
Make 8x8 attribute areas by a logic to detect attribute table address; the name table address is then stored in a latch, which is connected to a CHR RAM in the cartridge, and is activated (and the CIRAM disabled) when the attribute table is being accessed, instead of using the actual attribute table addresses.
Although masking out attribute reads is easy, the rest of the logic is complex enough you'll want to use a CPLD. But yes, 2K of RAM plus a CPLD plus the internal VRAM would let you get 8x8 attribute zones.
If you have some kind of RAM with one read-only bus and one write-only bus (I don't know if any such thing exist), then with a little bit of decoding logic you might be able to make it so that writes to PRG addresses $1xxx are copied into the CHR RAM (although then you can't write CHR RAM through the PPU).
Dual-ported RAM exists, but is exceptionally expensive. It also can be faked using a CPLD. You wouldn't want it to be mapped into the same area as the mirrors of the NES's internal WRAM, however.

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