Got some BSX hardware donated from skaman: An Itoi Bass No1 cart, a BSX BIOS cart, and a FLASH memory pak.
First of, the FLASH chip pinout (as from datasheet, and with the datapak slot connector pins in right column):
Code:
LH28F800SUT FLASH CHIP
1 3V/5V cn.34
2 /CE1 cn.51
3 NC (A21) cn.50
4 NC (A20) cn.48
5 A19 cn.46
6 A18 cn.44
7 A17 cn.42
8 A16 cn.40
9 VCC cn.31,32
10 A15 cn.38
11 A14 cn.29
12 A13 cn.35
13 A12 cn.11
14 /CE0 (GNDed) cn.1,2,61,62
15 VPP cn.30 <--
16 /RP (reset/powerdown) cn.47
17 A11 cn.41
18 A10 cn.43
19 A9 cn.39
20 A8 cn.37
21 GND cn.1,2,61,62
22 A7 cn.13
23 A6 cn.15
24 A5 cn.17
25 A4 cn.19
26 A3 cn.21
27 A2 cn.23
28 A1 cn.25
---
29 NC
30 NC
31 /BYTE cn.52 <--
32 A0 cn.27
33 D0 cn.3
34 D8 cn.60 <--
35 D1 cn.5
36 D9 cn.58
37 VCC cn.31,32
38 D2 cn.7
39 D10 cn.56
40 D3 cn.9
41 D11 cn.54
42 GND cn.1,2,61,62
43 VCC cn.31,32
44 D4 cn.4
45 D12 cn.53
46 D5 cn.6
47 D13 cn.55
48 GND cn.1,2,61,62
49 D6 cn.8
50 D14 cn.57
51 D7 cn.10
52 D15 cn.59
53 RDY/BSY (ready/busy) cn.12 <--
54 /OE cn.14
55 /WE cn.16
56 /WP cn.18 <--
The newly discovered pins are VPP, /BYTE, RDY/BSY, /WP, and D8-D15 (which formerly haven't been known if/where they were mapped on the datapak slot). Accordingly, the update datapak slot pinout is as so (btw. mechanically, the connector resembles a 50pin Compact Flash connector, with same 1.27mm pin pitch, but with 62 pins instead of 50 pins):
Code:
BSX Datapak Slot
1 GND
2 GND
3 D0
4 D4 (with cap to gnd)
5 D1 (with cap to gnd)
6 D5
7 D2
8 D6
9 D3
10 D7
11 A12
12 RDY/BSY (NC) (connected in BSX-BIOS cart)
13 A7
14 /RD via 33 ohm R2
15 A6
16 /WR via 33 ohm R3 (VCC in SA1)
17 A5
18 /WP (VCCed)
19 A4
20 - (in FLASH cart: via 47kohm R1 to VCC)
21 A3
22 via R4 to VCC (47kOhm) (NC in mempak)
23 A2
24 via R5 to GND (47kOhm) (NC in mempak)
25 A1
26 via R6 to GND (47kOhm) (NC in mempak)
27 A0
28 - (in FLASH cart: via 47kohm R2 to VCC)
29 A14
30 VPP (5V) (GND in SA1)
31 VCC (5V or 3.3V)
32 VCC (5V or 3.3V)
33 via R7 to VCC (47kOhm) (NC in mempak)
34 3V/5V (GNDed=5V)
35 A13
36 REFRESH to SNES.pin.33
37 A8
38 A15 rom SNES.A16 SNES.pin.41
39 A9
40 A16 rom SNES.A17 SNES.pin.42
41 A11
42 A17 rom SNES.A18 SNES.pin.43
43 A10
44 A18 rom SNES.A19 SNES.pin.44
45 SYSCK SNES.pin57 (and via R1 to SNES.pin.2 EXPAND) (100 ohm)
46 A19 rom SNES.A20 SNES.pin.45
47 /RESET (or VCC in some cart/slots)
48 A20 rom SNES.A21 SNES.pin.46
49 -
50 A21 rom SNES.A23 SNES.pin.48 (NOT SNES.A22 !!!)
51 /CS (from MAD-1A.pin1, SA1.pin81, MCC-BSC.pin23)
52 /BYTE (GNDed) (VCC in SA1 carts)
53 D12 (NC)
54 D11 (NC)
55 D13 (NC)
56 D10 (NC) ... pins here are D8-D15 (on PCBs with 16bit databus)
57 D14 (NC)
58 D9 (NC)
59 D15 (NC)
60 D8 (NC)
61 GND
62 GND
For the Itoi cart (with SA1 chip), writing to FLASH/ROM isn't supported: VPP is GNDed (no programming voltage), and /WR is VCC (no write signal at all, not even for issuing the FLASH chip detect commands). There's also another PCB with SA1 and datapak slot, but I haven't checked (the PCB photos) yet to see if they are wired the same way... there's a small chance that it could support flash writing (but it's also quite possible that the SA1 chip can't output /WR signals for the FLASH/ROM area at all). Apropos, small update to some SA1 pins:
Code:
SA1 pins
...
80 ROM./CS0.A22 (pin12=/CS in Itoi, pin1=A22 in Derby)
81 ROM./CS1 (datapak in Itoi)
82 GND?
83 VCC
84 GND?
85 GND-or-VCC ;GND in Derby, VCC in Itoi (maybe related to 1-2 rom chips)
...
The Derby cart uses pin80 as A22 (for ROMs with up to 8MByte; although the Derby ROM isn't actually that large) (and doesn't use any /CS and /OE pins; the ROM's /CS and /OE are just GNDed).
The Itoi cart uses pin80/pin81 as ROM and FLASH chip selects (and also has ROM /OE GNDed). And pin85 is wired differently, maybe switching between 8MB and 2x4MB ROM mode (although, /CS0 and A22 should be always low for first 4MB, so there's no real difference... unless the timing for outputting /CS0 and A22 is slightly different).
---
And, the MCC-BSC chip pinout (memory controller in BSX BIOS cart):
Code:
MCC-BSC
1 D7 snes.53
2 CIC1 snes.55
3 CIC2 snes.25
4 CIC3 snes.56
5 CIC0 snes.24
6 GND
7 /WR snes.54 via R8 (33 ohm)
8 /IRQ snes.18 for /FLASH.BSY
9 A23 snes.48
10 A22 snes.47
11 A21 snes.46
--
12 A20 snes.45
13 A19 snes.44
14 A18 snes.43
15 A17 snes.42
16 A16 snes.41
17 GND
18 A15 snes.40
19 A14 snes.39
20 A13 snes.38
21 A12 snes.37
22 REFRESH snes.33 why?
--
23 /ROM.CS rom.26 (aka rom.22)
24 /PSRAM.CS psram.22
25 /FLASH.WE mempak.16
26 /PSRAM.OE psram.24
27 VCC
28 GND
29 MA15 mempak.38
30 MA16 mempak.40
31 MA17 mempak.42
32 MA18 mempak.44
33 MA19 mempak.46
--
34 MA20 mempak.48
35 MA21 mempak.50
36 /FLASH.BSY mempak.12 with pullup R1
37 /FLASH.WP mempak.18
38 NC ? maybe /EXTMEM select?
39 VCC
40 /FLASH.CS mempak.51
41 /SRAM.CS mm1134.7
42 /RESET snes.26
43 SYSCK snes.57
44 /RD snes.23 via R7 (390 ohm)
The /IRQ and /FLASH.BSY and /FLASH.WP pins are certainly unexpected. And no idea what REFRESH is used for. Pin38 might be chipselect for some (uninstalled) extra memory chip, possibly sharing address lines and /OE /WE with other chips. CIC is basically just an intergrated CIC, but don't know if it could be swtched from NTSC to PAL mode (by changing one of the GNDed pins maybe), and don't know if it's somehow smashing the memory mapping (eg. when a PAL console doesn't output the expected NTSC CIC signal).
And the MCC chip's I/O ports... the (current) description in fullsnes.htm doesn't match up with the actual memory mapping, but the
http://wiki.superfamicom.org/snes/show/BS-X+MMIO seems to contain mostly correct mapping info for ports 025000h-0C5000h, the document formatting can be a bit confusing (I needed to gaze at it four about 5 hours before getting the impression that I understood what it's all about; however, the actual memory mapping is really a bit confusing hardware-wise... the mapping hardware is very simple, but nethertheless confusing because it comes up with many different bit-combinations... and for understanding that part, the superfamicom.org doc has been really helpful, I am glad that I didn't need to figure out all that stuff myself).
So far, I've verified parts of the superfamicom.org info (only checked the upper 32K halves at 8000h-FFFFh yet), and my test result did match up with the info (except one missing detail for PSRAM in HiROM mapping: The upper 32K-halves of the data at 40h-7Fh/C0h-BFh are ALSO mirrored to 00h-3Fh/80h-7Dh).
And the other MCC bits are working as so...
Code:
0:005000h FLASH Ready IRQ Flag (0=None, 1=IRQ) (write any value to acknowledge)
0:015000h FLASH Ready IRQ Enable (0=Disable, 1=Enable)
0:025000h..0C5000h see superfamicom.org
0:0D5000h Unknown (could be FLASH /WP pin... but doesn't really work as so)
0:0E5000h Write any value to apply changes to Page0:025000h..0D5000h (ONLY those 12 bits) (read: always 0)
0:0F5000h MCC Register Page (0=Page0, 1=Page1)
1:005000h..0E5000h Unknown (fifteen read/write-able bits)
1:0F5000h MCC Register Page (0=Page0, 1=Page1) (same as 0:0F5000h)
For Page0:025000h..0D5000h, reading returns to APPLIED value (not the most recently value). For 0:005000h, reading returns the IRQ flag, writing acknowledges it. For 0:0E5000h, reading seems to return always 0, and writing applies the most recently written bits. For 0:015000h, 0/1:0F5000h, and 1:005000h..0E5000h, reading just returns the most recently written value (no applying needed for those bits).
Reading page1 is slightly bugged: Upper/lower 8bits are swapped (reading 1:005000h..075000h returns what was written to 1:085000h..0F5000h, and vice-versa). That's making it somewhat impossible to read the MCC Register Page bit (or in fact, reading works fine, but without knowing its value, one cannot know if one needs to read it from 0F5000h or 075000h; and when knowing its value, then it would be pointless to read it at all).
For the /FLASH.WP pin, the pin seems to be always LOW=write protected. That protection should affected ONLY flash sectors that are flagged as protected, so writing should still work as long as there aren't any such flagged sectors, anyways, there SHOULD be a way to toggle the MCC's /FLASH.WP output pin...
I've tried setting 0:0D5000h, and also tried writing increasing numbers to the Page1 bits, but didn't manage to change /WP yet... at the moment I am running out of ideas... aside from checking if I've wired the scope to the correct pin.
The fifteen bits at 1:005000h..0E5000h are also still mysterious, some guesses would be a timeout counter for the FLASH Ready IRQ (not checked yet), or unlocking /WP (didn't seem to work out), or changing the memory mapping (though they didn't affect my mapping test for the memory areas at 8000h-FFFFh, no matter if I set all fifteen bits to all ones, or leave them at their power up default (all zeroes)).
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