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PostPosted: Mon Apr 29, 2019 11:29 am 
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Using that wikibooks page seems to be a bad idea - some of it looks more or less right, but it looks more like a game hacking tutorial, and it's claiming the snes to be organized in 4kbyte pages? There isn't anything in the console or cartridges bound to 4kbyte boundaries, except maybe some pirate copiers were bound to 4kbyte boundaries back in the 1990'ies.
In the snes world, the term "page" is sometimes used to refer to a 256 byte memory area (specifically in case of the cpu's "direct page" addressing mode).

If you are using hirom, then your rom is located at C00000-FFFFFF, aka bank C0-FF. Apart from that, you'll also need to understand the CPU's memory accessing modes, and the consoles's mapping for RAM and I/O ports.

If you are using battery backed SRAM for saving game positions, then you will also need to know how and where to access that memory... and, yes, some carts are using 74139 chops for the SRAM mapping, but that's normally happenig behind your back, and software programmers don't have to care about whether that mapping is done via MAD1 or 74139 or other ways.

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PostPosted: Mon Apr 29, 2019 12:11 pm 
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koitsu wrote:
illuminerdi wrote:
I think my real problem is that I don't understand SNES memory addressing well enough. I'm reading through https://en.wikibooks.org/wiki/Super_NES ... memory_map and it doesn't quite make sense. If banks are notated as $00-$FF, that's still only an 8-bit bitmask, so selecting any of those banks requires 8 bits and thus can be done without needing to multiplex.

That page is terrible. I don't know what it is with people and the SNES memory map -- there have been I think at least 10 different "attempts" to describe it, and all of them are just downright terrible (many are too verbose because they're trying to cover too many things at once).

For a better understanding of the main two memory modes/layouts -- known as mode 20 (LoROM) and mode 21 (HiROM), which are effectively two separate types of PCBs -- I suggest seeing 3 pictures Tepples drew somewhat recently. One is a "summary" (i.e. general concept of the entire memory space as a whole), the other two are more precise/specific to each mode (these are the two I suggest understanding): viewtopic.php?p=235113#p235113

There are tons of revisions of these PCBs based on what features you want (battery-backed SRAM, etc.), and others which have unique tweaks/etc. applied to them in certain ways (those are a per-game thing, so do not get hung up on them or focus on them; understand the commonplace memory layouts first).


Yeah I'm actually quite familiar with the differences between LoROM vs HiROM - I've made repro games using both boards, donors, aftermarket PCBs, etc. I just don't understand *WHY* some games are LoROM vs HiROM, and how the memory address chips factor into the equation, which is what I'm trying to get a better understanding of. I'll check the links you provided, thanks!


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PostPosted: Mon Apr 29, 2019 1:10 pm 
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Ok so I was way off - I thought the MAD-1 and/or 74'139 chips were required to address portions of memory within a game's ROM even in scenarios when the game uses a single ROM with no SRAM on the PCB. Apparently that is not the case and they are only required when a cart either uses multiple ROM chips and/or an SRAM chip, for switching between the ROMs or enabling write in the SRAM.

I thought it was a function of size - larger games tended to also be longer, so they tended to support saving, so you would often see 16/24/32Mbit games use a MAD-1 or 74LS139, but the demux wasn't necessary for accessing different portions of the ROM, it was just because those games also had SRAM and so the demux was needed in order to enable saving since there wasn't a pin for /WE on the SNES cart edge.


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PostPosted: Mon Apr 29, 2019 2:15 pm 
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nocash wrote:
it's claiming the snes to be organized in 4kbyte pages?

I can't think of anything in the Super NES that uses 4 KiB pages. But VRAM is organized in 4 Kiword (8 KiB) pages, at least according to OBSEL and BG??NBA.

illuminerdi wrote:
I just don't understand *WHY* some games are LoROM vs HiROM

I think it was whatever a particular game's programmers found more convenient. My guess is that HiROM has that nice linear address space, whereas LoROM makes it easier to have DBR pointing at both a table in ROM and the low RAM and PPU registers.

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PostPosted: Mon Apr 29, 2019 3:29 pm 
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tepples wrote:
illuminerdi wrote:
I just don't understand *WHY* some games are LoROM vs HiROM

I think it was whatever a particular game's programmers found more convenient. My guess is that HiROM has that nice linear address space, whereas LoROM makes it easier to have DBR pointing at both a table in ROM and the low RAM and PPU registers.

I wouldn't expect either of you to know the answer to this question, so I guess being the "historian" around here I'll have to:

In early days (or rather, as "late" as November 1993), Nintendo's own documentation for mode 20/LoROM indicated it only supported up to 16mbit ROM size. For larger (up to 32mbit), you had to use mode 21/HiROM. I have actual on-paper versions of older manual releases, which is how I know this. Said documentation also did not cover PCB/board types, nor mode 25. This also helps explain in part why things like 24mbit mode 20/LoROM games were "a pain in the butt" for emulation folks as well as some console copiers. This paragraph would make more sense if I could show you the depictions in the latest manual vs. older manual, but obviously I cannot risk doing that. I likewise suspect Nintendo came out with newer PCB revisions that "offered" more addressing space particularly for mode 20/LoROM than previous, but you had to know what PCB board model to request for your game, etc...

So in short: the choice was mainly dictated by ROM size for a long time, followed later by "whatever the programmer's found more convenient".


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PostPosted: Mon Apr 29, 2019 6:20 pm 
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illuminerdi wrote:
I'm actually reasonably familiar with the functionality of mux/demux as a concept (I've worked in networking and telecommunications for much of my professional life)
That made me wonder if mux/demux are used differently in analog telecoms versus digital memory mappers... the first thing I came across was a schematic like this:
Code:
              .-------.                    .-------.
      --> Sel0|       |            --> Sel0|       |
      --> Sel1|       |            --> Sel1|       |
              | - - - |                    | - - - |
   -----> In0 |       | Out ---------> In  |       | Out0 ----->
   -----> In1 |  Mux  |                    | Demux | Out1 ----->
   -----> In2 |       |                    |       | Out2 ----->
   -----> In3 |       |                    |       | Out3 ----->
              '-------'                    '-------'
I had never realized that one could wire a mux & demux in pairs as shown above - now I do better underunderstand why they are called "mux" and "demux".
I guess that kind of circuit would be most useful with analog (de-)multiplexers, allowing to pass four analog inputs to four analog outputs, by using only a single cable (plus some patchwork to ensure that the additional Sel0+Sel1 signals are always the same on both sides (unless one wants to "swap" the signals, eg. passing In0 to Out2)).

Digital (de-)multiplexers could be theoretically used the same way, but I have never seen that in practice (it would be more common to use a serial transfer for that purpose (or just to use four separate wires)).
Instead of pairing mux with demux, digital circuits are more commonly using only either one, for implementing this or that logic trickery. Especially demultiplexers can be used fairly differently with different thinking:
Code:
              .-------.
   -----> Sel0|       |
   -----> Sel1|       |
              | - - - |
      --> /En |       | Out0 ----->
              | Demux | Out1 ----->
              |       | Out2 ----->
              |       | Out3 ----->
              '-------'
Here the 'main input' is usually wired to the Sel0+Sel1 pins, and the original Input pin is merely used as an optional extra feature (some datasheets are referring to it as "/Enable" pin instead of "Input" pin) (some circuits are simply having that pin grounded to make it "always enabled", or, the snes cartridge circuit.is having it wired to /CART (cart memory select) signal, so that's closer to the original purpose where "In" is getting forwarded to "Out'N").

illuminerdi wrote:
I thought it was a function of size - larger games tended to also be longer, so they tended to support saving, so you would often see 16/24/32Mbit games use a MAD-1 or 74LS139, but the demux wasn't necessary for accessing different portions of the ROM, it was just because those games also had SRAM and so the demux was needed in order to enable saving since there wasn't a pin for /WE on the SNES cart edge.

The /OE and /WE signals are called /RD and /WR on the SNES cart edge. The 74139 logic is used for generating the separate /CE chip enables in carts that contain more than one memory chip. like ROM + SRAM.
Or, yes, back then it was also a "function of size": if a game was too large for the "small" ROMs of those days, then they needed to use two or more ROM chips, and generate separate chip selects for each chip.

koitsu wrote:
tepples wrote:
illuminerdi wrote:
I just don't understand *WHY* some games are LoROM vs HiROM

I think it was whatever a particular game's programmers found more convenient. My guess is that HiROM has that nice linear address space, whereas LoROM makes it easier to have DBR pointing at both a table in ROM and the low RAM and PPU registers.

I wouldn't expect either of you to know the answer to this question, so I guess being the "historian" around here I'll have to...

Technically, tepples' answer has fairly well nailed down the main advantages/disadvantages.
Historically, yes, nintendo's documentation and naming has probably contributed a good bit to confusion about the snes memory map.

The other thing that is making snes memory confusing is the lorom mapping with the 32Kbyte chunks mixed with mirrors of the system area - that can be comfortable for small programs, but it's confusing at first glance, and it does somewhat require a "2-dimensional" memory map with 16bit offset in one dimension and 8bit bank in the other dimension (as opposed to, say, gameboy advance, where you have only one dimension ranging from 0 to FFFFFFFFh).

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PostPosted: Mon May 13, 2019 6:47 pm 
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Hi again- I disappeared because I was busy with other work, but I've had some free time and am returning to the project. I found a really helpful resource:

http://randombazz.blogspot.com/2011/09/ ... oding.html

For me, this really helped me to understand the 74139/138. It definitely helped to write down the truth tables and compare to see what results were wanted by the SNES and how to work backwards from there for creating your own replacement.

Hope this helps!

Also, if anyone has any insight, I don't understand the placement of the transistor in the above warosu picture. I think the main part that confuses me is tying the 5V rails to the base through a reverse bias diode to the base, and another with the 5V rail going to the collector but also the output of one of the demux (can the demux pull this low when the input signals are correct?)


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