Sunsoft 3 testing

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krzysiobal
Posts: 649
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Sunsoft 3 testing

Post by krzysiobal » Thu Feb 13, 2020 8:46 am

Looks like there is no pinout nor description of chip, so high time to crush the piggy bank and buy patient for testing.

Code: Select all

                 .---\/---.
       +RESET -> | 01  42 | -- VCC                
 (n)       M2 -> | 02  41 | <- EXT /IRQ (n/c)
 (nr) CPU A11 -> | 03  40 | <- CPU D7  (nr)        
 (nr) CPU A12 -> | 04  39 | <- CPU D6  (nr)        
 (nr) CPU A13 -> | 05  38 | <- CPU D5  (nr)        
 (n)  CPU A14 -> | 06  37 | <- CPU D4  (nr)        
 (n)  /ROMSEL -> | 07  36 | <- CPU D3  (nr)        
 (n)  CPU R/W -> | 08  35 | <- CPU D2  (nr)        
 (r)  PRG /CE <- | 09  34 | <- CPU D1  (nr)        
 (n)  CIR A10 <- | 10  33 | <- CPU D0  (nr)            
 (r)  CHR /CE <- | 11  32 | -> /RAM-CE (n/c)
 (nr) PPU A10 <- | 12  31 | -> RAM+CE  (n/c)
 (n)  PPU A11 -> | 13  30 | <- PPU A13 (n)       
 (n)  PPU A12 -> | 14  29 | <- PPU /RD (n)          
 (r)  CHR A16 <- | 15  28 | -> /IRQ    (n)    
 (r)  CHR A15 <- | 16  27 | -> PRG A14 (r) 
 (r)  CHR A14 <- | 17  26 | -> PRG A15 (r) 
 (r)  CHR A13 <- | 18  25 | -> PRG A16 (r) 
 (r)  CHR A12 <- | 19  24 | -> PRG A17 (n/c) 
 (r)  CHR A11 <- | 20  23 | -> /PRG A17 (n/c)      
      GND     -- | 21  22 | -> $f800.4 (n/c)
                 `--------'
                  SUNSOFT-3
                  
[...XPPPP} at $f800


Notes:
* Mapper 067
* Pins marked as n/c were not connected in subject cartridge [Fantasy Zone II (J)].
* Pin 1 connected to the following M2-based reset detector. However, even if M2 stops toggling, PRG/CHR banks still can be changed, and nothing is held in reset. Maybe it is just used to initalize some internals of the chip.

Code: Select all

   M2-+-|<---+--pin1
      |      |
      +--1k--+
             |
            82p
             |
            GND
* Pin 22 reflects the value of $f800.4, no matter what address CPU is reading
* Purpose of pin 23 is probably to allow two 128k PRG-ROMS to be connected. If they have /CE+/OE then PRG1/CE=PRG2/CE=PRG/CE, PRG1/OE=PRG A17, PRG2/OE=/PRG A17. If they have single /CE then using external OR gate PRG1/CE = PRG/CE || PRG A17, PRG2/CE = PRG/CE || /PRG A17
* Pins 31/32 are active for $6000-$7fff
* Writing to $c800 or $d800 does NOT cause IRQ to be acked. Instead, writing to any of those registers ACKS:
$8000, $9000, $a000, $b000, $c000, $d000, $e000, $f000 (looking at the IRQ handler in Fantasy Zone 2 it indeed writes to $8000 to ack)
* Pin 41 is input, internally pulled-up to +5V. I don't quite know how it works, but when tied to GND (witk 1k resistor for safety), the game does not boot. After more testing it looks like it is responsible for some kind of external interupt? Here are my testing scenarios:
1) $d800.4=1 and this pin goes to GND, /IRQ is immediatelly triggered and cannot be acked in any way. The only way is to disconnect pin 41 from GND and then write to $x000 (x=$8..f$)
2) if $d800.4=0 and this pin goes to GND, IRQ is not asserted. Setting $d800.4 to 1 immediatelly triggers /IRQ and it cannot be acked in any way. The only way is to disconnect pin 41 from GND and then write to $x000 (x=$8..f$)

Maybe along with pin 22, it can be used to communnicate with some external chip that can also assert interrupts (additional audio chip?)

lidnariq
Posts: 9025
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Sunsoft 3 testing

Post by lidnariq » Tue Feb 18, 2020 12:12 am

krzysiobal wrote:
Thu Feb 13, 2020 8:46 am
* Pin 1 connected to the following M2-based reset detector. However, even if M2 stops toggling, PRG/CHR banks still can be changed, and nothing is held in reset. Maybe it is just used to initalize some internals of the chip.

Code: Select all

   M2-+-|<---+--pin1
      |      |
      +--1k--+
             |
            82p
             |
            GND
It's too fast to be a reset detector. 1 kΩ × 82 pF = 82 ns. Also, M2 goes Hi-Z during reset, not high. So this has to be something that's for asymmetrically delaying M2: falling edges should coincide, but rising edges are delayed by roughly 82ns.

Maybe the internal registers are transparent latches instead of clocked, and this pulse shaping means that the signal received on pin 1 will indicate that the data bus is valid during the entire write? Pin 2, M2, might only be used for the IRQ.

The Vs. Platoon board ("2UNI-E05" per one archived eBay auction, but I think the pictures on John's Arcade and Playchoice.Riemenschnieder are probably "-E04") has a 74LS04 and no obvious diode, so it has to work there despite the 2A03's 17/24 or 19/24 M2 duty cycle. It's conceivable that R1 (1kΩ) and C3 (unknown, small, green, ceramic) somehow serve as the same pulse shaper there.

krzysiobal
Posts: 649
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Re: Sunsoft 3 testing

Post by krzysiobal » Tue Feb 18, 2020 11:25 am

lidnariq wrote:
Tue Feb 18, 2020 12:12 am
Maybe the internal registers are transparent latches instead of clocked, and this pulse shaping means that the signal received on pin 1 will indicate that the data bus is valid during the entire write? Pin 2, M2, might only be used for the IRQ.
My mistake, the resistor is connected to VCC, like this:

Code: Select all

            VCC
             |
            1k
             |
   M2-+-|<---+--pin1
             |
            82p
             |
            GND
And trully, it delays the rising edge a little (or rather - makes its slew rate lower). Anyway, I did some tests and when pin 1 is permanently grounded:
* Writing to registers does not have any effect,
* CPU reads does not decrement the IRQ counter
* Pins 31/32 are not asserted when accessing $6000-$7fff

It means that in fact, pin 1 is internally treated as the true M2. Wonder what is the purpose of pin2 then.
BTW. The diode has blue stripe, not black, so maybe a zener?

BTW2. You wrote on wiki that
`$f800.4 = (unused by existing hardware) External interrupt enable`.
I think this is just ordinary latch bit, how it is used depends on the designer imagination.

--

I disconnected pin 2 from M2 and when tied to GND, also writing to registers does not have effect, IRQ counter does not work and RAM is not asserted, but when tied to VCC it all works.. Hmm.
Either rising edge on pin 1 must be used as clock to IRQ counter (and value on PIN2 need to be high to make it count), or vice versa..
Last edited by krzysiobal on Tue Feb 18, 2020 11:48 am, edited 1 time in total.

lidnariq
Posts: 9025
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Sunsoft 3 testing

Post by lidnariq » Tue Feb 18, 2020 11:45 am

krzysiobal wrote:
Tue Feb 18, 2020 11:25 am
Anyway, I did some tests and when pin 1 is permanently grounded:
* Writing to registers does not have any effect,
* CPU reads does not decrement the IRQ counter
* Pins 31/32 are not asserted when accessing $6000-$7fff

It means that in fact, pin 1 is internally treated as the true M2. Wonder what is the purpose of pin2 then.
[...]
I disconnected pin 2 from M2 and when tied to GND, also writing to registers does not have effect, IRQ counter does not work and RAM is not asserted, but when tied to VCC it all works.. Hmm.
Either rising edge on pin 1 must be used as clock to IRQ counter (and value on PIN2 need to be high to make it count), or vice versa..
Sounds like pin 1 and pin 2 are actually used together to act as the enable to the ASIC, and the two are ANDed together...
BTW. The diode has blue stripe, not black, so maybe a zener?
If so, you should be able to see it on an oscilloscope during operation. The zener voltage would have to be low enough for it to be relevant ... otherwise it'd just be acting like an ordinary diode.

One source I found insinuates that the convention of blue=zener only applies to the SMT miniMELF form factor. But this isn't something I have any background in.
BTW2. You wrote on wiki that
`$f800.4 = (unused by existing hardware) External interrupt enable`.
I think this is just ordinary latch bit, how it is used depends on the designer imagination.
... I misread your original commentary about d800 and somehow saw f800.

There's no chance that there's an OR gate there and that that pin is actually PRG A18?
no matter what address CPU is reading
I guess not.

krzysiobal
Posts: 649
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Re: Sunsoft 3 testing

Post by krzysiobal » Tue Feb 18, 2020 12:42 pm

Sounds like pin 1 and pin 2 are actually used together to act as the enable to the ASIC, and the two are ANDed together...

When pin1 is tied to VCC and pin2 to the M2, IRQ counter does not decrease (but RAM/Registers works).
So probably IRQ counter is clocked by edge on pin 1 and also pin 2 need to be high for that to work and registers are latched when falling edge of AND

When pin1 is tied to VCC and pin2 to the M2, WRAM/Registers/IRQ COunter also works. You're right - everything needs AND of them both to work.

There's no chance that there's an OR gate there and that that pin is actually PRG A18?
When writing 0 or 1 to $f800.4, pin 22 stayed in the corresponding level for the whole time when CPU was reading $0000-$ffff, while pins 23/24 danced.

lidnariq
Posts: 9025
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Sunsoft 3 testing

Post by lidnariq » Tue Feb 18, 2020 2:20 pm

krzysiobal wrote:
Tue Feb 18, 2020 12:42 pm
When pin1 is tied to VCC and pin2 to the M2, WRAM/Registers/IRQ COunter also works. You're right - everything needs AND of them both to work.
I suppose the last piece of trivia is whether both together are required to assert PRG /CE, or if only pin 2 is used there. Not the least bit important, of course.

krzysiobal
Posts: 649
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Re: Sunsoft 3 testing

Post by krzysiobal » Tue Feb 18, 2020 2:33 pm

None of them is used to assert PRG /CE - they can be both 0. Just /ROMSEL and R/W are taken into account.

lidnariq
Posts: 9025
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Sunsoft 3 testing

Post by lidnariq » Tue Feb 18, 2020 2:36 pm

Oh, wacky. That means that in the Vs. System daughterboard the ROMs are enabled for the entire cycle.

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