"Emulating" the NES in Hardware

Discuss emulation of the Nintendo Entertainment System and Famicom.

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parth
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"Emulating" the NES in Hardware

Post by parth » Sun Oct 26, 2008 1:17 am

I know this is kind of impractical for most purposes, but I'm interested in essentially designing the NES (including the CPU, PPU, Memory, NTSC Video Encoder, etc. ) in hardware (using Verilog on an FPGA, to be specific).

Right now I'm kind of overwhelmed with the amount of work it would take to get something like this working, but I think it can be done.

Do any of you have any tips/good documents to look at on how I should go about designing something like this? For starters, I'll need a really detailed document on how the 2A03 CPU works. I already have a SDRAM Memory Controller and Video Encoder working.

Thanks a bunch,
Parth

P.S. I posted this on the NESdev forum, but I've realized that this is probably a better place to put it, because my job will be very similar to emulating)

tepples
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Re: "Emulating" the NES in Hardware

Post by tepples » Sun Oct 26, 2008 4:23 am

parth wrote:I know this is kind of impractical for most purposes, but I'm interested in essentially designing the NES (including the CPU, PPU, Memory, NTSC Video Encoder, etc. ) in hardware (using Verilog on an FPGA, to be specific).
Kevin Horton has done this once. He put both the NES and the mapper in the FPGA because otherwise, he would have had to put a bunch of level shifters in the signal path to convert all signals between 3.3 V and 5.0 V at the cart edge.
For starters, I'll need a really detailed document on how the 2A03 CPU works.
6502.org should help.

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teaguecl
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Post by teaguecl » Sun Oct 26, 2008 10:24 pm

Parth, I have a background in Verilog and VHDL and would be willing to contribute to an open source project like what you describe. I unfortunately don't have the time to commit to run such a project, but could contribute from time to time.


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jwdonal
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its definitely possible

Post by jwdonal » Sun Feb 21, 2010 5:40 pm

I am implementing the NES on an FPGA using SystemVerilog and the CPU and PPU are functional (albeit with some minor bugs). I am working on the APU now. You can find my website in my profile. Unfortunately, I had to take the site down for reasons described here.

I am hoping to be able to bring the site back up soon though. The NNSA is trying my patience with this silly review process they are making me go through. I'm considering just printing out my site contents to PDF and sending it to my manager for derivative classification. This would allow me to legally (and temporarily) "side-step" the review process until I get some response back from NNSA. They've had my design notes for 4 months already...it shouldn't take that long to review. Haha.

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jwdonal
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i'm back up!

Post by jwdonal » Tue Feb 23, 2010 7:44 pm

My site is back up now! :)

https://rm-rfroot.net/nes_fpga/

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