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My goal is to make a limited set focused on a target volume, and close enough to target frequencies to help with a low byte count. Be careful/deliberate here. With DPCM, volume is the same as harmonic distortion. Trying to represent something too loud generates slew rate distortion, and the naive a...

Thanks for clearing that up. Now I just wonder where the register is when pin6=1. My guess is rising edge of pin 9 or pin 23... although I guess it could still be pin 19, even though it's otherwise unused. Right now, pin6=1 really looks like pin22 = "/READ" in the same way that pin6=0 has pin9=R/W. ...

No, no.. I just wanted to point that latching occurs on edge, not on level. On the rising edge of pin 19 chip checks for proper values of other inputs to determine if latching should be done or not. Right, but is it specifically a rising edge of pin 19 (/ROMSEL)? Or just anything ending the write c...

I know it's not the least bit satisfying to use someone else's work instead of doing it yourself, but I've generated a comprehensive set of every possible triangle-wave-on-DPCM: viewtopic.php?p=154032#p154032

I checked if there seems to be other registers, by issuing a write of different value at the second bank address, also reading with different values of Pin22/23 and it does not affect the currently described functionality - everything seems to be the same (PRG banking, mirroring, data in/data out p...

While debugging code I noticed that the return address for a subroutine was pushed to $00:00FE - $00:00FF instead of $00:01FE - $00:01FF . As far as I have read, SNES should use page 1 for stack just like NES, but still it seems to go to zero page. If you're in Emulation (65C02) mode, that's correc...

Because the current mapper definition assigns D6 and D7 to mirroring control and this bit without additional wires does not have influence to mirroring, I preferred to not use it. That's a good reason. Unrelatedly, do any pins other than 8, 9, 19, 20, and 28 affect where the mapper register is? I w...

Don't see good reason what's the point of enabling ROM there. Maybe the line can be reused to control additional RAM and pins 22/23 can be CPU-A13/CPU-A14? Now that you mention it, it is fairly reminiscent of the UNROM512 memory map, where there's a 16KB window to access the banking register, and a...

... so in conclusion, it does have bus conflicts, for absolutely no good reason? I spent a few minutes trying to figure out if there was an obvious way to rewire pins 6,8,9,19,22,23,28 to do anything else useful at all, but I don't see anything... Also looks like pin 11 could be coaxed into providin...

mkwong98 wrote: ↑

Tue Feb 18, 2020 7:42 pm

And what other HW defects can you think of?

Emulate CIC negotiation failure with 50% odds each time someone opens a file

... I just realized that in the test above I was only using HDMA to set OPT locations, which necessarily mustn't be offset by the visible scanline, because the OPT data is used for the entire screen.



... for whatever it's worth, 256 - 119 = 137

CHR lines are more-or-less safe to corrupt. PRG lines are mostly not. The easiest to describe would be to randomly switch CHR and nametables between open bus and correct. In practice, this means that random slivers will be of some portion of the " open bus " picture, because a temporarily missing na...

Oh, wacky. That means that in the Vs. System daughterboard the ROMs are enabled for the entire cycle.

When pin1 is tied to VCC and pin2 to the M2, WRAM/Registers/IRQ COunter also works. You're right - everything needs AND of them both to work. I suppose the last piece of trivia is whether both together are required to assert PRG /CE, or if only pin 2 is used there. Not the least bit important, of c...

Anyway, I did some tests and when pin 1 is permanently grounded: * Writing to registers does not have any effect, * CPU reads does not decrement the IRQ counter * Pins 31/32 are not asserted when accessing $6000-$7fff It means that in fact, pin 1 is internally treated as the true M2. Wonder what is...