Search found 1240 matches

by 93143
Sat Oct 24, 2020 1:19 am
Forum: SNESdev
Topic: Flashlight effect
Replies: 5
Views: 266

Re: Flashlight effect

Doesn't the halving not happen for fully transparent subscreen pixels (ie: constant colour)?
by 93143
Thu Oct 22, 2020 1:55 am
Forum: SNESdev
Topic: [demo] SNES Sonic
Replies: 178
Views: 49399

Re: [demo] SNES Sonic

I think by mentioning Blast Processing people are just being sarcastic and are not really serious about it, as that term can mean anything (or... nothing at all other than advertising jargon) True. But there are only a couple of ways someone knowledgeable could seriously claim the Mega Drive has "b...
by 93143
Wed Oct 21, 2020 8:24 pm
Forum: SNESdev
Topic: [demo] SNES Sonic
Replies: 178
Views: 49399

Re: [demo] SNES Sonic

Yes it does. It just goes at half the speed of the MD version (or less if the MD is using H40 mode). I'm assuming you're talking about "blasting" colours into CRAM via DMA. You can do that on SNES too. It's tricky, but you can actually display a fullscreen uncompressed 15-bit RGB image on SNES using...
by 93143
Tue Oct 20, 2020 5:54 am
Forum: SNESdev
Topic: How does Tales of Phantasia and Star Ocean scale sprites on stock hardware?
Replies: 26
Views: 1413

Re: How does Tales of Phantasia and Star Ocean scale sprites on stock hardware?

The SNES does have 128 KB of WRAM. Perhaps that's what he meant - I believe psycopathicteen has demonstrated smooth sprite rotation by calculating everything before it's needed, in parallel with the game, and dumping the results into WRAM so they're available when required.
by 93143
Tue Oct 20, 2020 1:45 am
Forum: SNESdev
Topic: Why did official SA1 games use no features of the chip?
Replies: 7
Views: 641

Re: Why did official SA1 games use no features of the chip?

Normal SNES DMA speed, basically. Coordination between the two processors is a bit involved, but the intent is to get as close as possible to pretending the source data is in CHR format.
by 93143
Mon Oct 19, 2020 11:50 pm
Forum: SNESdev
Topic: Why did official SA1 games use no features of the chip?
Replies: 7
Views: 641

Re: Why did official SA1 games use no features of the chip?

Weirdly enough, no. The SA-1 has a special feature called "character conversion", which allows you to use the SA-1 to draw graphics in a linear bitmap format and then DMA the result to VRAM as SNES bitplane graphics. Basically the SA-1's DMA system converts the source data into SNES CHR format on th...
by 93143
Mon Oct 19, 2020 12:45 am
Forum: SNESdev
Topic: Can layer 1 and 2 display 2bpp graphics?
Replies: 11
Views: 874

Re: Can layer 1 and 2 display 2bpp graphics?

So you'd do this in order to make sprites load 2BPP graphics? Yes. One practical problem with uploading 2bpp CHR data for use as 4bpp sprite cels is that you have to skip 8 words (16 bytes) in VRAM after each 2bpp tile for the 2 planes you aren't using. If you can store or render the graphics in NE...
by 93143
Sun Oct 18, 2020 4:11 pm
Forum: SNESdev
Topic: Can layer 1 and 2 display 2bpp graphics?
Replies: 11
Views: 874

Re: Can layer 1 and 2 display 2bpp graphics?

It is possible to transfer 2bpp graphics into a 4bpp format in VRAM, by exploiting the way VRAM access works to only write half the bitplanes in the destination memory. This would save resources upstream, but in VRAM it would take the same amount of space as 4bpp graphics.
by 93143
Thu Oct 08, 2020 1:37 pm
Forum: SNESdev
Topic: CA65 Memory Map Config and Header for 32Mb ROM
Replies: 12
Views: 653

Re: CA65 Memory Map Config and Header for 32Mb ROM

I don't know how Nintendo handled it on-cart, or how heuristic-based loading works in emulators and flash carts, but there's zero reason LoROM as a concept couldn't handle nearly 8 MB. There's no SNES-side hardware reason why the ROM in banks $00-$7D has to be a mirror of $80-$FD. Look at the old no...
by 93143
Wed Sep 30, 2020 9:29 pm
Forum: SNESdev
Topic: CA65 Bit-shift During Compilation Isn't Working Properly
Replies: 22
Views: 3152

Re: CA65 Bit-shift During Compilation Isn't Working Properly

For Mode 7, the PPU ignores the BG1/2 tilemap/tiledata offset registers, so the data starts at $0000. Everything else can be put wherever.
by 93143
Tue Sep 29, 2020 3:18 pm
Forum: SNESdev
Topic: Design guidance for 3D Engine on SuperFX
Replies: 39
Views: 10472

Re: Design guidance for 3D Engine on SuperFX

¿¿F-zero with hills and objects aside?? :beer: Oh, I've got tons of ideas, including those two. The game would still be largely Mode 7-based, but not entirely, and there are a bunch of cool tricks you can do if you're willing to special-case stuff. Also, I think the physics and AI could be far bett...
by 93143
Tue Sep 29, 2020 12:32 am
Forum: SNESdev
Topic: Design guidance for 3D Engine on SuperFX
Replies: 39
Views: 10472

Re: Design guidance for 3D Engine on SuperFX

How would you even get a real Super FX devcart? Don't those things cost thou$and$ on eBay? Or are you going to go Randy Linden and gut a Super FX cartridge? By "devcart", I mean something built new around a real Super FX pulled from a real game. Something I can program repeatedly, but not something...
by 93143
Mon Sep 28, 2020 8:37 pm
Forum: SNESdev
Topic: Design guidance for 3D Engine on SuperFX
Replies: 39
Views: 10472

Re: Design guidance for 3D Engine on SuperFX

One thing that worries me about RedGuy's Super FX is that he apparently had to fiddle with it a lot to get it running at about the correct speed . He remarks on the difficulty of getting the parallel processing timing correct here . In principle it should be possible to build an exact functional rep...
by 93143
Fri Sep 25, 2020 10:08 pm
Forum: SNESdev
Topic: Design guidance for 3D Engine on SuperFX
Replies: 39
Views: 10472

Re: Design guidance for 3D Engine on SuperFX

I believe the SA-1 was the only chip complex enough to not be compatible in the first place. Super FX + MSU1 worked on the old FPGA.
by 93143
Fri Sep 25, 2020 2:26 pm
Forum: SNESdev
Topic: Design guidance for 3D Engine on SuperFX
Replies: 39
Views: 10472

Re: Design guidance for 3D Engine on SuperFX

IIRC the current version uses a new FPGA that's capable of running the SA-1 and MSU1 simultaneously. The original couldn't do that.