Search found 3192 matches

by Zepper
Tue Sep 11, 2018 7:41 pm
Forum: NESemdev
Topic: Emulator update and question about timing and microcodes
Replies: 8
Views: 7494

Re: Emulator update and question about timing and microcodes

I remember of Disch discussing about queue/dequeue PPU events after a certain amount of CPU cycles. Did he vanish from the forum... too?
by Zepper
Tue Sep 11, 2018 7:36 pm
Forum: NESemdev
Topic: Sprite evaluation timing
Replies: 4
Views: 7964

Re: Sprite evaluation timing

I'm still rewriting my sprite evaluation logic, but I have a few notes. Hope it helps. 1. The sprite evaluation starts at PPU cycle 65. On odd cycles, data is read from primary OAM (sprite ram). On even cycles, the buffered data is written to the secondary OAM (32 bytes long). 2. Steps 1 and 2 refer...
by Zepper
Sun Sep 09, 2018 7:07 am
Forum: NESemdev
Topic: NOP interrupt polling
Replies: 17
Views: 13708

Re: NOP interrupt polling

I just assumed that mixing of IRQ and NMI in Blargg's source comment was a typo. I treat them the same in the branch opcodes anyway. No, it wasn't. Did you read the entire test source code? Here's the FULL description... ; A taken non-page-crossing branch ignores IRQ during ; its last clock, so tha...
by Zepper
Fri Sep 07, 2018 9:07 pm
Forum: NESemdev
Topic: NOP interrupt polling
Replies: 17
Views: 13708

Re: NOP interrupt polling

Would it help folks if I asked Blargg to chime in here (unlikely), or if I asked him to read this thread + posted a verbatim answer/reply on his behalf? He left the forums a long time ago for reasons of his own, and we should respect him. The test file is 5-branch_delays_irq , from cpu_interrupts_v...
by Zepper
Fri Sep 07, 2018 8:47 pm
Forum: NESemdev
Topic: NOP interrupt polling
Replies: 17
Views: 13708

Re: NOP interrupt polling

Sour wrote:There is nothing different about NOP vs other instructions in terms of the IRQ timing, afaik, though.
You're right.
by Zepper
Fri Sep 07, 2018 8:39 pm
Forum: NESemdev
Topic: NOP interrupt polling
Replies: 17
Views: 13708

Re: NOP interrupt polling

Quote from the sources... ; A taken non-page-crossing branch ignores IRQ during ; its last clock, so that next instruction executes ; before the IRQ. Other instructions would execute the ; NMI before the next instruction. That means the 3rd cycle. I'm just curious what is meant by "polling" here? Do...
by Zepper
Fri Sep 07, 2018 2:50 pm
Forum: NESemdev
Topic: NOP interrupt polling
Replies: 17
Views: 13708

Re: NOP interrupt polling

JonteP wrote:Yes, I forgot to mention that it's the $ea NOP I'm talking about. So, is this dependent on the NOP opcode?
For some reason, this is the NOP opcode used for the test. Nothing more.
by Zepper
Fri Sep 07, 2018 7:27 am
Forum: NESemdev
Topic: NOP interrupt polling
Replies: 17
Views: 13708

Re: NOP interrupt polling

( INTs = NMI and IRQ acknowledgement) 1. There are different NOPs due to the different addressing modes. You're (probably) taking opcode $EA as NOP. The quick answer here is YES - you should poll INTs normally. 2. If branch is taken, the 3rd cycle is executed without polling INTs. If the page was c...
by Zepper
Thu Aug 30, 2018 2:41 pm
Forum: NESemdev
Topic: How to use blargg's instr_test-v5
Replies: 19
Views: 16462

Re: How to use blargg's instr_test-v5

You must fetch the RESET vector from the PRG ROM data at $FFFC (low byte) and $FFFD (high byte). This test ROM starts at $E000, not $8000. Why does it start at $E000. Isn't it a mapper 0? It's unrelated . The RESET vector is a 16-bit value that sets up the initial PC register. In other words, it po...
by Zepper
Thu Aug 30, 2018 1:04 pm
Forum: NESemdev
Topic: How to use blargg's instr_test-v5
Replies: 19
Views: 16462

Re: How to use blargg's instr_test-v5

You must fetch the RESET vector from the PRG ROM data at $FFFC (low byte) and $FFFD (high byte).
This test ROM starts at $E000, not $8000.
by Zepper
Thu Aug 30, 2018 12:52 pm
Forum: NESemdev
Topic: New CPU test ROM
Replies: 34
Views: 44000

Re: New CPU test ROM

Version 6. 8-)
by Zepper
Sun Aug 19, 2018 5:36 pm
Forum: NESemdev
Topic: Emulator failing ppu_vbl_nmi test #2
Replies: 2
Views: 6244

Re: Emulator failing ppu_vbl_nmi test #2

If I'm not wrong, it's the same question here.
viewtopic.php?f=3&t=17663
by Zepper
Fri Aug 17, 2018 6:20 pm
Forum: NESemdev
Topic: NMI timing
Replies: 8
Views: 8617

Re: NMI timing

According to my log above, NMI is triggered at scanline 241 (first vblank scanline) dot 1. Is that wrong? You know about the CPU-PPU alignment, right? Well, during my tests, I had to request NMI 1 PPU cycle earlier. In other words, at line 240 cycle 341. Technically, it would be the same , but I cl...
by Zepper
Thu Aug 16, 2018 6:18 pm
Forum: General Stuff
Topic: Is the SNES a realible console? So worried about reliability
Replies: 20
Views: 7386

Re: Is the SNES a realible console? So worried about reliabi

I have my Super NES since 199X. It had a problem with the board (PPU burnt due to the power ac). Other than that, it's working up to the present day like a charm.