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lord_Chile
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question about loopy docs

Post by lord_Chile » Wed Jun 28, 2006 3:30 pm

Thanks to disch for explain loopy docs, i understand format, but i can see a exception here:

2000 write:
t:0000110000000000=d:00000011

2006 first write:
t:0011111100000000=d:00111111


t:1100000000000000=0
---??? what mean this line??, it is not = d (data).
It is =0?, i dont understand
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Disch
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Post by Disch » Wed Jun 28, 2006 3:48 pm

t:1100000000000000=0

That means the high 2 bits are filled with 0 ($FFFF becomes $3FFF)

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lord_Chile
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question about emus

Post by lord_Chile » Fri Jun 30, 2006 3:12 pm

I assume (ppu_ctrlreg_1 And H4) =0...
Vram access test of blargg said that "SansaNES" (my emu) fail with error 6 (blargg_ppu_tests_2005.09.15b).
Error 6 is "Palette read should also read VRAM into read buffer".

Then, now i am analyzing blargg asm code in order to see where my knowledge and logic fails, please if any expert can help me
and see where i fail in my analyze, i will be happy, thanks. I start from reset...

Code: Select all

set_vram_pos:
'this set vram_pos at $2f00 + A
'i wont write it for space

reset:
      lda   #6
A=#$6	      

      sta   result
result= #$6

      lda   #$12
A=#$12

      jsr   set_vram_pos
vram_pos=$2F12

      lda   #$9a
A=#$9A

      sta   $2007
VRAM[$2F12]=#$9A
vram_pos= incremented to $2F13

      lda   $2007
It is not palette, then i use a "vram buffer"
A="vram buffer"
vram_buffer=VRAM[$2F13]  ("i dont know what contains buffer")
vram_pos= incremented to $2F14

      lda   #$3f
      sta   $2006
      lda   #$12
      sta   $2006

vram_pos=$3F12

      lda   $2007   ; fills buffer with VRAM hidden by palette 
It is palette, then  i dont load from "vram buffer"
A=VRAM[$3F12]  ("now, i dont know what contains A")
vram_pos=incremented to $3F13

      lda   #$13    ; change back to non-palette addr to enable buffer
A=#$13

      jsr   set_vram_pos
vram_pos=$2F13

      lda   $2007
It is not palette, then i use a "vram buffer"
A= VRAM[$2F13]  (last vram buffer did contains it)
vram_buffer=VRAM[$2F13]  (last vram pos is $2F13 no?)
vram_pos= incremented to $2F14

"Here i assume that blargg says: if A=#$9a then test is passed.
      cmp   #$9a

"But VRAM[$2F13] never can contains #$9A 
since i never did send #$9A to it. VRAM[$2F12] contains #$9A.

Then test never is passed, but Nintendulator and FCEUdx did pass this test. 
What am i doing bad??? ps: First beta schpune of disch, 
didnt pass this test. The test contains errors?

      jsr   error_if_ne
Good day to nesdev people. Lord..
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UTFSM Sansano programmer.. lord_Chile
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-_pentium5.1_-
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Re: question about emus

Post by -_pentium5.1_- » Fri Jun 30, 2006 7:11 pm

lord_Chile wrote:I assume (ppu_ctrlreg_1 And H4) =0...
Vram access test of blargg said that "SansaNES" (my emu) fail with error 6 (blargg_ppu_tests_2005.09.15b).
Error 6 is "Palette read should also read VRAM into read buffer".

Then, now i am analyzing blargg asm code in order to see where my knowledge and logic fails, please if any expert can help me
and see where i fail in my analyze, i will be happy, thanks. I start from reset...

asm code deleted
Just for reference, the answer is here: http://nesdev.com/bbs/viewtopic.php?t=1721
This signature intentionally contains no text other than this sentence.

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lord_Chile
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question about cpu cycles

Post by lord_Chile » Thu Jul 13, 2006 11:14 am

Thanks disch, thanks guys.

Today i bring a new question. My emu didnt pass many blargg timing test, then i decide increase accuracy. I am programming my cpu emu cycle per cycle. I get official manual 6502.

It says:

Code: Select all

Example 5.3: Illustration of implied addressing

clockcycle	addrbus     PC           data bus      comments
1	PC	PC+1	opcode	  fetch opcode


2	PC+1	PC+1	new opcode ignore new opcode;
	 			  decode old opcode


3	PC+1	PC+2	new opcode fetch new opcode;
				  execute old opcode
Notes: 2nd cycle: the memory fetch is worthless and any PC increment is supressed.


Then my questions:

1.- for what we can see three cpu cycles, if implied addressing is 2 cpu cycles?
2.- the third cycle is taken in account for calculate cpu cycles?
3.- the third cycle is for internals operations of cpu but it is not from implied addressing?
4.- do i execute opcode instruction (lda, etc) immediatelly after fetch and decode it or i do buffer execution?

I did imagine a type of buffer for execute old opcodes, but if a new opcode is not executed, then
old opcode never execute: example

LDA
#$40
(I did pass for here but i didnt execute LDA, only fetch it)
NOP
"nop" is new instruction, i fetch and save it, i know addressing for this instruction too.
now i execute old opcode LDA and addressing mode.
(imagine that LDA be last instruction and nop doesnt be here: LDA never will be executed)

Implementing this is overhead and i am not sure that 6502 behaviour is like it.
Can you giving clear to my ideas??
Good day to nesdev people. Lord..
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UTFSM Sansano programmer.. lord_Chile
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Quietust
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Post by Quietust » Thu Jul 13, 2006 12:30 pm

6502 instructions are pipelined by 1 cycle - when you do "LDA #$FF", the first cycle grabs the opcode (A9), the second cycle loads the operand (FF), and the 3rd cycle copies the operand (FF) into the accumulator while fetching the next opcode. For emulation purposes, the "copy operand to accumulator" can be performed at the end of the 2nd cycle (actually emulating the pipelining is unnecessary, since the software can't tell the difference AND it'd be slower).
Quietust, QMT Productions
P.S. If you don't get this note, let me know and I'll write you another.

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lord_Chile
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directx question

Post by lord_Chile » Wed Jul 19, 2006 2:51 pm

i am new in direct x. I was using gdi (but it's slow). setpixel was the procedure in order to put a pixel on screen.

But, emulator authors use pixel per pixel render?
what procedure set a pixel on screen using direct x?
do i use direct 3d? im confused
or i use direct draw for render?
i wanna good render speed.
i will use directx 8.
Good day to nesdev people. Lord..
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UTFSM Sansano programmer.. lord_Chile
Saludos a la Sede JMC de la UTFSM... Viña del Mar, CHILE

tepples
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Re: directx question

Post by tepples » Wed Jul 19, 2006 4:11 pm

lord_Chile wrote:But, emulator authors use pixel per pixel render?
what procedure set a pixel on screen using direct x?
do i use direct 3d? im confused
[...]
i will use directx 8.
In DirectX 8, you build a texture representing the screen as an array of pixels, and then you draw the texture to the screen. DirectX 8 doesn't have DirectDraw except as a wrapper around Direct3D.

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lord_Chile
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question about ppu timing

Post by lord_Chile » Sun Jul 23, 2006 2:28 pm

I did read brad taylor documents, but im a little confuse. About sprite 0 hit and ppu timing.

1.- ppu fetch valid data during 256 ppu clocks and at end of clock 256 it send valid pixel data to video output for render? or ppu fetch one valid data and immediatelly send it to video output pin?

2.- Sprite 0 hit with no transparent background collision is detected using temporary memories (in fetch time)? or when video contents are being drawed (in rendering real time)?

3.- At end of 256 ppu clock do i wait for "one delay (16 ppu cycles - fine horizontal scroll)" in order to wait for sprite 0 collision?, or when i wait for this delay?
Good day to nesdev people. Lord..
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UTFSM Sansano programmer.. lord_Chile
Saludos a la Sede JMC de la UTFSM... Viña del Mar, CHILE

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lord_Chile
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what can i do?

Post by lord_Chile » Sun Jul 23, 2006 9:44 pm

i hope a answer thanks
Good day to nesdev people. Lord..
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UTFSM Sansano programmer.. lord_Chile
Saludos a la Sede JMC de la UTFSM... Viña del Mar, CHILE

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Disch
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Re: question about ppu timing

Post by Disch » Mon Jul 24, 2006 5:28 am

lord_Chile wrote:or ppu fetch one valid data and immediatelly send it to video output pin?
I don't know how "immediate" it is. But the PPU will output 1 pixel every PPU cycle. (1 cycle = 1 pixel). Since there are 256 rendering cycles, this means 256 pixels are output.
or when video contents are being drawed (in rendering real time)?
This is right.

Sprite 0 hit will happen on the cycle the sprite 0 pixel is being rendered.
3.- At end of 256 ppu clock do i wait for "one delay (16 ppu cycles - fine horizontal scroll)" in order to wait for sprite 0 collision?, or when i wait for this delay?
This delay does not really affect sprite 0 hit at all. (It's not even really a "delay").

The PPU has to have a tile fully ready to draw before it can actually start drawing it. Because of this, tiles need to be loaded some time before they're actually rendered.

Here is a little diagram to help portray the idea:

Code: Select all

Scanline    Cycles      What is happening
--------------------------------------
0           320-327     PPU loading 1st tile for scanline 1 (no pixels output)
0           328-335     PPU loading 2nd tile for scanline 1 (no pixels output)
0           336-341     PPU performing dummy reads          (no pixels output)
1           0-7         PPU loading 3rd tile for scanline 1 (output proper pixels from 1st+2nd tiles)
1           8-15        PPU loading 4th tile for scanline 1 (output proper pixels from 2nd+3rd tiles)
Once the tiles are loaded, they're stored in a temporary shift register until the pixels are actually output.

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lord_Chile
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problem with sprites coord

Post by lord_Chile » Wed Sep 13, 2006 3:09 pm

My emu fails when i load super mario bros. I can see background, sprite 0 hit has good y coord, but mario sprites has 248=y coord everytime. I dont see super mario sprite. Ballon fight works fine. what can be the problem??
Good day to nesdev people. Lord..
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UTFSM Sansano programmer.. lord_Chile
Saludos a la Sede JMC de la UTFSM... Viña del Mar, CHILE

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ok another question

Post by lord_Chile » Sun Sep 17, 2006 8:58 am

my problem was sbc inst of cpu. i fix it.

Im trying emulate mapper 7 for battletoads. All is right, but one screen mirroring is emulated with errors. I dont understand... if bit says: mirror from $2400, or mirror from $2000 what is the difference?..

If is mirror from $2400:
1.- If i write to nametable address $2003.. whaT HAPPEN?

If is mirror from $2000:
1.- If i write to nametable address $2403.. whaT HAPPEN?

Actually i copy all $2400 nametable area to another 3 nametables
if is mirror from $2400..

and if is $2000 copy all from $2000 to another nams.. But it appears that there are errors in my logic because text are joined on screen when i execute game.. example:

Licensed by Nintendo
A Rare Production..

I dont want a rare production, i dont know from where comes it.

Someone can explain me one screen mirroring with more detail???
Good day to nesdev people. Lord..
Author of nothing =P
UTFSM Sansano programmer.. lord_Chile
Saludos a la Sede JMC de la UTFSM... Viña del Mar, CHILE

tepples
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Post by tepples » Sun Sep 17, 2006 9:26 am

The "Mirror from $2000" and "Mirror from $2400" descriptions are misleading. What really happens is that all four pages $2000, $2400, $2800, and $2C00 are mirrored from page LO or page HI depending on the mapper setting.

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lord_Chile
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question about mmc1 and mmc3

Post by lord_Chile » Tue Sep 19, 2006 12:55 pm

1.- mmc1 ports are 1 bit.. But if i wanna reset register 0 i would write eight times to register 0, no? But what values are written to bits 5 and 6 (unknow bits)??

$8000 - $9FFF (Register 0)

RxxCFHPM

When i write first 5 bits, register is ready to execute.. i think..
Someone can explain this to me, please?

2.- mmc3 bankwitch are 8kb for prg.... but i have problems switching vrom..

If command is 3, The $8001 page number assume 1024kb vroms pages??
by example if rom have 2 pages of chr, each one 8kb, Then max value for $8001 is (2*8)-1=15???
Good day to nesdev people. Lord..
Author of nothing =P
UTFSM Sansano programmer.. lord_Chile
Saludos a la Sede JMC de la UTFSM... Viña del Mar, CHILE

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