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 Post subject: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 7:15 am 
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If the IRQ line is pulled low and the interrupt disabled flag is true, how long is it before it is returned to high again (assuming there is no subsequent CLI operation and the flag stays set)

I'm sorry if this question has been answered a million times before but I've trawled the forums and the wider internet searching for an answer!


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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 7:32 am 
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Your question is not clear to me.

matthewtatum wrote:
..how long is it before it is returned to high again..


What is returned to high? .. Edit.. Bregalad's answer is better and makes the most sense based on what your question must mean.


Last edited by Movax12 on Fri Feb 20, 2015 7:33 am, edited 1 time in total.

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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 7:32 am 
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Forever ?

External devices are supposed to pull the IRQ line low when they want to have attention of the processor, and then the processor is supposed to, with the help of memory-mapped I/O, acknownledge the IRQ, and tell the device it can release the IRQ line. Thus even if the 'I' flag is set, the IRQ is never missed, the device keeps waiting for the processor to get attention until an acknowledge happens.


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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 8:18 am 
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Thanks for the replies

I'm asking this question from the point of view of an emulator developer.

I am trying to figure out how to emulate IRQs correctly and I (probably naively) thought that I could do something like this:

After finishing latest instruction, check to see if IRQ has happened and if it has:
If 'I' is set ignore it and forget the IRQ ever happened;
else handle interrupt (Push return address and status register onto stack and move PC to IRQ vector)

I have just started looking at implementing an MMC3 mapper and it's dawning on me that my naive assumptions are probably wrong. Looking at blargg's MMC3 tests there seem to be several cases where CLI is called followed by some code checking that "pending" IRQs have been serviced.

What I'm trying to understand is if an IRQ happens and the 'I' flag is set, does my CPU code need to remember that the IRQ happened and service it when the 'I' flag is next clear?


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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 8:46 am 
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matthewtatum wrote:
What I'm trying to understand is if an IRQ happens and the 'I' flag is set, does my CPU code need to remember that the IRQ happened and service it when the 'I' flag is next clear?

Of course ! Imagine how useless IRQs would be otherwise...


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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 9:03 am 
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Yeah, you can't forget about IRQs just because they aren't supposed to be serviced right away. IIRC, the CPU tests for IRQs every instruction.

As for pulling the IRQ line back up, that's up to the device that pulled it low, and the most common approach is to implement an "IRQ acknowledgement" register, so the program itself can let the device know that the IRQ has been handled.


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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 9:46 am 
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Level 0 interrupts (/IRQ) are level-sensitive. They recur as long as the interrupt priority bit (I) is 0 and something is pulling the /IRQ line low.

Level 1 interrupts (/NMI), on the other hand, are edge-sensitive. As I understand it, there's a flip-flop inside the CPU that gets set whether /NMI transitions from high to low and cleared when the interrupt circuitry jumps to the NMI handler. This means that if some device holds /NMI low indefinitely, only one /NMI will happen. In the NES, this means that only one NMI will happen per frame, at the start of line 241 (NTSC and PAL NES) or 291 (Dendy), unless the program disables and reenables NMI through writes to PPUCTRL (port $2000) in the middle of vblank.


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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 10:05 am 
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OK thanks, it's starting to make sense now, I think the missing piece of the puzzle in my mind was acknowledgment of IRQs. I thought I had read somewhere that 6502 IRQs could not be acknowledged and therefore got confused. I couldn't understand what the lifecycle of an IRQ was without acknowledgment.

In the case of MMC3 it seems that writing to an even address in the range of $E000-$FFFE acknowledges IRQs, is that right?


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 Post subject: Re: IRQ Question on 6502
PostPosted: Fri Feb 20, 2015 1:23 pm 
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Of course, IRQs can (and should) be acknownledged. This is nothing NES or 6502 specific, also. What is specific is that there is only ONE IRQ in the 6502, most processor have many IRQs, typically connected to different devices/timers. On the 6502 you're supposed to test which device caused the IRQ by software. If multiple devices caused an IRQ simultanenously, then the CPU services and acknownledge first the most urgent, and then the less urgent.

NMI is different because of it's edge sensitiveness, but nevertheless they also have to be acknowneldged. The PPU is half-an exception because it auto-acknowledge at the end of the VBlank period even if you don't read $2002. Because they can't be missed and the can (normally) only be connected to one interrupt source, it's a different story. If you connect NMI to multiple interrupt source (like it's the case on the C64) then you can miss interrupts, and it kinda miss the point of a "non-maskable interrupt" I think. I also guess on the C64 you are only supposed to use one of the NMI sources at a time and disable the others.


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