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PostPosted: Mon Oct 22, 2018 9:06 am 
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This is a general question about PPU Registers and other special Registers (like gamepad $4016) that the 6502 processor uses.

Do the devices watch those memory locations? Or is the 6502 somehow told that those memory addresses aren't real and it should therefore send a signal somewhere along the bus?

I'm just trying to get a better understanding of how those registers work and what is actually going on under the covers when you hit one of those addresses.

Thanks,
Rick

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PostPosted: Mon Oct 22, 2018 9:13 am 
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When reading or writing an address, the 6502 drives low or high voltages on the address bus, 0 volts for a zero bit of an address or 5 volts for a one bit. Each device watches for patterns of low and high voltages on the address bus that correspond to the addresses assigned to that device. For $4000-$401F, this is a decoder on the CPU die. For ROM ($8000-$FFFF), RAM ($0000-$1FFF), and the PPU ($2000-$3FFF), a decoder outside the CPU does some of the work of generating enable signals.

The Super NES, on the other hand, has a concept of "those memory addresses aren't real" for B Bus addresses.


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PostPosted: Mon Oct 22, 2018 10:52 am 
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As far as the 6502 is concerned, everything is memory, from $0000 to $FFFF, but the reality is this is never the case in any machine, because there are other components the CPU needs to interact with besides memory for a computer to function. Some CPUs have dedicated ports for this kind of communication, but the 6502 doesn't, so it relies on something called memory-mapped registers.

The 6502 is completely unawhere of what exists in which addresses, so it will always behave like it's writing to or reading from memory. It's the devices themselves (or auxiliary circuits for these devices) that watch for patterns in the memory accesses the CPU does and intercept the writes to redirect the values being written to where they need to go. Reads can also be intercepted if a device needs to return values (such as the controller ports).


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PostPosted: Mon Oct 22, 2018 8:12 pm 
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So are the devices listening on the bus then? Does that value ever make it into memory, or does the device somehow stop the value from making it to that location in memory? What happens if the 6502 tries to write to or read from a memory location that just doesn't exist?

Thanks for your help

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PostPosted: Mon Oct 22, 2018 8:21 pm 
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A value written to a particular address makes it into memory only if there's a memory that listens for writes to that address. If no memory is listening at any given address, the write makes it into no memory. This process of "listening" may be split between two separate circuits: a "decoder" that tells the memory when to listen and the memory itself.

One RAM in the Control Deck listens for CPU writes to $0000-$1FFF, ignores bits 12 (value $1000) and 11 (value $800), and completes the write.

The other RAM in the Control Deck listens for PPU writes while the cartridge enables it. (Most cartridges enable it at $2000-$3EFF. Some never enable it; one enables it for the whole $0000-$3EFF space.) If it is enabled, it takes bits 9-0 from the PPU and bit 10 from the cartridge's mirroring circuit (which usually corresponds to bit 10 or 11 from the PPU) to form the address for the write.

PRG RAM in the Game Pak, if present, usually listens for CPU writes to $6000-$7FFF. RAM in the Famicom Disk System listens for writes to CPU $6000-$DFFF.

CHR RAM in the Game Pak, if present, usually listens for CPU writes to $0000-$1FFF. Sometimes it listens for writes to $2000-$2FFF, particularly in games using 4-screen VRAM.


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PostPosted: Mon Oct 22, 2018 9:37 pm 
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battagline wrote:
So are the devices listening on the bus then?

Any device with memory-mapped registers has to listen to the bus, yes.

Quote:
Does that value ever make it into memory

Memory-mapped registers are usually mapped to locations that don't contain RAM, but it's possible for them to overlap, in which case the value goes to the device and into memory as well. I can't remember any instances of this on the NES, but it does happen with the Master System:

SMS Power! wrote:
Because the control registers overlap in the memory map with a RAM mirror, this mirrored RAM allows the last value written to each register to be read back (from the RAM copy). The registers are, however, strictly write-only. Overwriting the RAM mirror at another address will not affect mapping.

Quote:
or does the device somehow stop the value from making it to that location in memory?

Devices can disable memory chips whenever they want if they have control over said chips (e.g. a mapper can enable/disable in-cartridge RAM, but not the RAM inside the console), but usually they just avoid overlaps.

Quote:
What happens if the 6502 tries to write to or read from a memory location that just doesn't exist?

Writes go nowhere, since no one is listening to them, reads normally return open bus. Open bus is when no devices put anything in the data bus, so the last value that went through there persists and gets returned. It's normally the last byte of the instruction being executed (e.g. if you do LDA $627B you'll get $62 in the accumulator, because that's the last byte that went through the data bus when the CPU read the instruction from ROM).


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PostPosted: Mon Oct 22, 2018 10:51 pm 
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Tangent:
tokumaru wrote:
in which case the value goes to the device and into memory as well. I can't remember any instances of this on the NES, but it does happen with the Master System:
NINA-001 (the other half of mapper 34) puts its registers at $7FFD, $7FFE, and $7FFF, overlapping the cart RAM. The choice of addresses is kinda reminiscent of the SMS's mapper.


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PostPosted: Mon Oct 22, 2018 11:55 pm 
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On cartridges like NROM, would you get open bus if you read an unused address like $7FFF?


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PostPosted: Mon Oct 22, 2018 11:56 pm 
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Yes.


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PostPosted: Fri Oct 26, 2018 7:25 am 
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Note that the NES CPU itself is also a sound chip, and does handle its own sound registers. It also has a Sprite DMA feature, that will read a page of memory and repeatedly write to address $2004. These features are internal to the NES CPU itself, and are not found in other 6502 processors.

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PostPosted: Wed Nov 07, 2018 5:16 am 
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Your decoder has to look at the right bits (pins) to determine when to enable the peripheral and allow traffic between the CPU and the peripheral. My super simple 64kB PRG ROM setup requires a 1-bit register to select which 32kB half of the ROM I want the system to see at $8000-$FFFF. Since $8000-$FFFF corresponds to the cartridge ROM when read, it's a convenient place to put your mapper/any external cart hardware registers. What I need to watch for are the following conditions:
1. CPU adress pin 15 is high (pin 50 on a US/EU NES Cart connector). This means that the CPU is doing something in the $8000-$FFFF range.
2. CPU Read/Write pin is low, meaning it's a write (pin 14 on the Cart connector).

When both of these conditions are true, the register can be enabled to take whatever is coming on the data bus. During this, ROM for example should be disabled because even though the CPU is in the $8000-$FFFF range, it's in write mode and not read mode. But when this is not accounted for in your design, a Bus conflict can occur.


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PostPosted: Wed Nov 07, 2018 10:26 am 
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Can internal ram be disabled and redirected to on-cart ram?

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PostPosted: Wed Nov 07, 2018 10:45 am 
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A 2Kx8 SRAM in the Control Deck on the PPU bus is almost always mapped at $2000-$2FFF for nametables. But it can be disabled, as seen in four-screen mappers (e.g. Gauntlet), ROM nametable mappers (e.g. After Burner), and MMC5.

CPU RAM at $0000-$07FF (mirrored to $0800-$1FFF), not so much.


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PostPosted: Wed Nov 07, 2018 10:58 am 
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Hmmm, I was just curious if you could swap the zero page around.

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PostPosted: Wed Nov 07, 2018 11:11 am 
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Zero page can be swapped. If you're curious, ask in SNESdev about TCD.


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