Introducing the VeriSNES (FPGA-based SNES)

Discussion of hardware and software development for Super NES and Super Famicom.

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jwdonal
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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by jwdonal » Sun Dec 25, 2016 4:00 pm

First, Merry Christmas!

Second, new progress video is now available! Added support for 16x16 tile sizes for backgrounds!
https://youtu.be/kTT9v355Z4I

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by supermario4 » Mon Dec 26, 2016 7:14 pm

jwdonal wrote:First, Merry Christmas!

Second, new progress video is now available! Added support for 16x16 tile sizes for backgrounds!
https://youtu.be/kTT9v355Z4I
is this like the avs is this a hdmi snes but based on the snes jr rgb but maybe better?

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by getafixx » Thu Dec 29, 2016 8:03 pm

^^
I think if you'd bothered to read the first post in this thread that question would be answered already.

It's an FPGA SNES system, being designed from scratch. It has nothing to do with any RGB mods, but it is similar in concept to the AVS (which is also an FPGA system).

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by jwdonal » Fri Dec 30, 2016 10:21 am

New progress video. Enjoy!

https://youtu.be/LNrlmb6excw

In this video:
- Mode 5
- True Hires
- Pseudo-Hires
- Overscan
- Interlace

Note: Regarding my comments on Secret of Mana, I learned after I made the video that Secret of Mana uses direct color mode which I don't have implemented yet. So that explains at least some of the graphics weirdness. It also uses Mode 7 in the intro sequence which is why half of the screen is missing during part of the intro.

Thanks again to tepples for helping me with understanding the weirdness of mode 5!

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by Revenant » Fri Dec 30, 2016 5:41 pm

The "smushed" background on the Mode 0 screen is because the test normally displays a row of sprites both with and without sprite interlace (bit 1 of $2133). Enabling this also requires setting the normal interlace bit (bit 0), but this bit is only supposed to double the number of visible background lines in modes 5 and 6.

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jwdonal
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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by jwdonal » Fri Dec 30, 2016 5:57 pm

Revenant wrote:The "smushed" background on the Mode 0 screen is because the test normally displays a row of sprites both with and without sprite interlace (bit 1 of $2133). Enabling this also requires setting the normal interlace bit (bit 0), but this bit is only supposed to double the number of visible background lines in modes 5 and 6.
Awesome! Thanks for the tip. Much appreciated.

Now if I can ever get to working on sprites...haha. Nintendo really threw the kitchen sink (or two) at this sytem. So many features :shock: :shock: :shock:

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by paulb_nl » Sun Jan 01, 2017 8:53 am

Thanks for the videos. Its great seeing the progress.

How does the SNES actually output the 512 Hires mode? It outputs 341 dots per scanline which normally has 256 active pixels and I haven't been able to find how it can output 512 pixels per scanline.

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by tepples » Sun Jan 01, 2017 8:59 am

Each pixel is 4 master clocks long. In hi-res mode, it instead outputs each pixel for two master clocks.

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by paulb_nl » Sun Jan 01, 2017 9:42 am

So that means it outputs 682 dots per scanline in Hires mode right? Does the pixelclock get increased in Hires mode from 5 to 10MHz to be able to do that?

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by tepples » Sun Jan 01, 2017 9:51 am

Another way to view it is that the background video output is DDR (double data rate) in hi-res mode, changing on both rising and falling edges of the pixel clock. The sprite pixel still changes once every dot (4 master clocks).

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by paulb_nl » Sun Jan 01, 2017 10:47 am

Thanks!

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by jwdonal » Wed Jan 18, 2017 10:26 am

Hello all,

I haven't posted an update in a while but don't worry I've been hard at work! Here is the latest progress update demo:

https://youtu.be/1gNflzKp49o

In this video:
- Background Modes 2/4/6
- Offset Per Tile Logic
- 8x8 Multiply, 16x8 Multiply, 16/8 Divide
- 2 major bug fixes (1 graphical, 1 related to MDMA)
- Other misc

Enjoy!

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by jwdonal » Wed Jan 18, 2017 11:55 am

I had a request for a Tetris Attack demo for offset per tile mode. Here it is!

https://youtu.be/hYb4REKBHZI

Enjoy!

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by magno » Mon Jan 23, 2017 12:40 am

I'm really excited to see that somebody could make true one of my dreams since 2006... A full SNES in a FPGA!! I always wanted to make something like this on my own, but using VHDL and Xilinx devices (I have got more than 15 years experience with both), and even started a similiar project in 2010, although my first module was a CVBS encoder which outputs FI-modulated PAL and NTSC signals. After that, I started to study the PPU, but it was far too complicated than expected, so I dropped.

By the way, are you planing to add some tweaks to improve SNES performance? I mean, it could be nice to have an "accuracy profile" and a "performance profile" in order to have a beefed-up SNES, but still compatible: faster WRAM access, DMA at full speed (i.e., at the maximum clock frequency your system works), FIFO-buffered byte transfers between CPU and APU for faster sample transfer, expanded VRAM size...


Hope we all can see this amazing project completed!

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Re: Introducing the VeriSNES (FPGA-based SNES)

Post by jwdonal » Mon Jan 23, 2017 2:01 am

Performance enhancements would certainly be possible since the hardware is fully programmable but the real question is what games would use them? The answer is none - at least not any official ones anyway. So while it's a cool thing to think about, there would really be no point in doing it.

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