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PostPosted: Sun Dec 11, 2016 1:43 pm 
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Location: UK (temporarily)
AWJ wrote:
I'm almost 100% certain that the bits of the BGnHOFS registers are actually split between the two chips that comprise the S-PPU: the low 3 bits are on PPU2, and the rest of the bits are on PPU1.
Oh, that would make the weird bit math much clearer.

It would mean the situation is something more nearly like:
new_coarse_nHOFS = (cur_write<<5) | (PPU1_HVOFS_LATCH>>3)
new_fine_nHOFS = PPU2_nHOFS_LATCH


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PostPosted: Sun Dec 11, 2016 1:56 pm 
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Excellent insight as always, AWJ.

We're certainly not doing ourselves a lot of favors by trying to implement the logic of both the PPU1 and PPU2 into the same class, as if they're one chip :/


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PostPosted: Sun Dec 11, 2016 5:09 pm 
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Location: NE Indiana, USA (NTSC)
byuu wrote:
one chip

Might lack of register splitting be one cause of the "Super Famiclone" behavior of the post-2/1/3 revision?


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PostPosted: Mon Dec 12, 2016 2:03 pm 
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Joined: Sat Jun 27, 2009 11:05 pm
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Location: New Mexico, USA
Thanks everyone. This was very helpful. After AWJ mentioned about the 3 LSbits being only in PPU2 things made a lot more sense. I actually already knew that those bits were only in PPU2 but I wasn't connecting that with its effect on the register assignment. Cool stuff!
lidnariq wrote:
By elimination, the X scroll registers have to be at least 11-bit, because when it's moved over into the fine X scroll the &4s bit isn't 0.
I just wanted to clarify on this...So you believe that all the scroll registers are 11-bit even though all the docs that I can find say they're 10-bit? It's not clear to me what purpose an 11-bit register would server. Only 10 bits are required for the maximum permissible scroll in any background configuration (I'm excluding $210D/E since those are also used for Mode 7).

From Anomie's regs.txt:
Code:
        x = The BG offset, at most 10 bits (some modes effectively use as few
            as 8).

        Note that all BGs wrap if you try to go past their edges. Thus, the
        maximum offset value in BG Modes 0-6 is 1023, since you have at most 64
        tiles (if x/y of BGnSC is set) of 16 pixels each (if the appropriate
        bit of BGMODE is set).
I think it would be very highly unlikely for Nintendo to insert a redundant flip-flop in the circuit design. A transistor saved is a penny earned. :D


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PostPosted: Mon Dec 12, 2016 2:19 pm 
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I mean, it's "11" bits because there's a "redundant" 3-bit latch in PPU2 for each horizontal scroll register. Keeping track of D2 on the first write so that it can be transfered later. It's there to make the API not suck.

Total number of latches is apparently
13 bits per horizontal scroll: seven coarse, three fine, and three for a 1-deep FIFO for fine scroll
10 bits per vertical scroll
eight bits shared across all eight registers in PPU1 as a 1-deep FIFO


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