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VHDL FPGA PPU Implementation.

Posted: Tue Jun 12, 2018 8:09 am
by laxer3a
Hi,

First post here.

Let me introduce myself (or my work actually) :
In 2010, I did a PPU implementation in VHDL but had no information at all at the time, and neither did I spent money on hardware to complete my project...
Still, my first try ended up with some pretty good result so far :
http://laxer3a.blogspot.com/
(Source was online, but I received like 3 mails in 8 years about it, mostly from student who wanted to use it ASAP as is. Replied to help, but nothing really forward after that...)

Since around a month, I started to work on it again, with proper timing information etc...etc...
My goals are multiple :
- Put it in open source.
- Have the code *as clean as possible* for anybody to maintain, proper documentation of trick or implementation details.
- Not bloated implementation. Minimalist.
- May be able to use the EXT port and create a nice modern extension for existing console. (For that, my implementation is currently limited to the DOT CLOCK. I plan to use DDR pumping to output the Hires512 mode)

Language used is VHDL. I noticed that other user on the forum have started their implementation too, they are welcome to contact me.

It will probably always be a *in progress* work, as documentation can always be improved, but anybody could do it from the source, or find issue and update the doc and the implementation.
Same for optimization or removal of redundant logic. For now things are getting pretty good.
I am entering the debug phase, my first goal is having first most of it working and then fine tune the details.

Anyway, I hope I am welcome here, and also hope to get the support from people around here about various details.


Cheers,
Laxer3A

Re: VHDL FPGA PPU Implementation.

Posted: Tue Jun 12, 2018 8:45 am
by thefox
Welcome to the forum!

Hosting the source on something like GitHub could get you a good amount of exposure.

Re: VHDL FPGA PPU Implementation.

Posted: Thu Jun 14, 2018 3:00 am
by laxer3a
Yeah... But I will wait until I get something fully functionnal until release or if I get fed up, at least it wont be lost.
(As I wrote earlier, putting it open source hasn't resulted in anything before...)

I have some questions (from many to come).

1/ I do remember somehow that sprites(Objects) are NOT displayed during the first scanline, am I correct ?
(I just browsed the Snes9X code, is like : int startline = (IPPU.InterlaceOBJ && GFX.InterlaceFrame) ? 1 : 0; )
And also, is it the same during interlace ?

2/ From the second scanline (BG Y=1), is the sprite line 1 is displayed or line 0 ? (lag of one line in coordinate)

But would be better to have an accurate and straight answer instead of writing test program / look at source code of emulators...

Re: VHDL FPGA PPU Implementation.

Posted: Thu Jun 14, 2018 7:46 am
by creaothceann
Line 0 is used to initialize the sprite engine. Before HBlank the sprites for line 1 are determined, and during HBlank their tiles are loaded from VRAM. Neither sprites nor backgrounds are displayed in line 0.

Afaik when a background has a vertical scroll value of 0, its first line would've been in screen line 0, but is skipped because line 0 is not displayed. I'd guess the same goes for sprites.

Re: VHDL FPGA PPU Implementation.

Posted: Fri Jun 15, 2018 1:12 am
by calima
Speaking from the programming side, SNES is exactly the opposite of NES where bg is correct and sprites are offset by one. SNES bg is offset by one and sprites are correct.

Re: VHDL FPGA PPU Implementation.

Posted: Sat Jun 16, 2018 8:39 am
by laxer3a
Just some small teaser, images are generated from H/V counter in digital from HDL simulation for now...
I am not back to the level I was in my first implementation many years ago but as all is implemented, it is just more about looking and fixing all the bugs one by one...

Here the first result I got in 24h after starting debugging :
- First RGB output. (No BG 1/2) Pixel reversed (H Flip not implemented + wrong pixel decoding order (stupid self, duh !)
- Fix pixel order.
(-Fix bug in tool that did not dump correctly the scroll register, was pointing to wrong map area)
- Desactivate pixel computation pipeline. (So implementation is shutoff to check that ALL pixels are coming.
- Fix bug in priority logic.


So here is the list of known bug yet not fixed for now :
- Loading state machine generate some glitch, that would explain the buggy tiles.
- Pixel pipeline is not working fully properly.

Let's see if I can keep the pace of fixing the glitch.
Hope you enjoy the progress as much as I do :-)

Re: VHDL FPGA PPU Implementation.

Posted: Mon Jun 25, 2018 1:32 am
by EmuandCo
laxer3a wrote:Hi,

First post here.

Let me introduce myself (or my work actually) :
In 2010, I did a PPU implementation in VHDL but had no information at all at the time, and neither did I spent money on hardware to complete my project...
Still, my first try ended up with some pretty good result so far :
http://laxer3a.blogspot.com/
(Source was online, but I received like 3 mails in 8 years about it, mostly from student who wanted to use it ASAP as is. Replied to help, but nothing really forward after that...)

Since around a month, I started to work on it again, with proper timing information etc...etc...
My goals are multiple :
- Put it in open source.
- Have the code *as clean as possible* for anybody to maintain, proper documentation of trick or implementation details.
- Not bloated implementation. Minimalist.
- May be able to use the EXT port and create a nice modern extension for existing console. (For that, my implementation is currently limited to the DOT CLOCK. I plan to use DDR pumping to output the Hires512 mode)

Language used is VHDL. I noticed that other user on the forum have started their implementation too, they are welcome to contact me.

It will probably always be a *in progress* work, as documentation can always be improved, but anybody could do it from the source, or find issue and update the doc and the implementation.
Same for optimization or removal of redundant logic. For now things are getting pretty good.
I am entering the debug phase, my first goal is having first most of it working and then fine tune the details.

Anyway, I hope I am welcome here, and also hope to get the support from people around here about various details.


Cheers,
Laxer3A
And I know your name from the good ol' GP32 scene. OpenSnes9xGP I think was the name...

Re: VHDL FPGA PPU Implementation.

Posted: Mon Jun 25, 2018 2:57 am
by laxer3a
Indeed. :-)
That is the first time I started to take a look at Snes9X, but Yoyofr did a lot more than me on the emulator.
(and we did it again for the PSP later on). The platform was so limited. (like 100 Mhz or so ?)

(And I update some progress)

Re: VHDL FPGA PPU Implementation.

Posted: Mon Jun 25, 2018 2:58 am
by laxer3a
I still have a timing glitch in the BG stuff I think.
Also I have one or two bugs remaining in the sprite logic.
Mode7 has been tested also.