PPU dual VRAM addressing
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Author:  hicks [ Wed Jan 02, 2019 9:14 am ]
Post subject:  PPU dual VRAM addressing

In the last few days I've been reading up on the SNES hardware (long way to go) and wondered if someone could clear up a question about the PPU VRAM. The schematic shows two 32k 8bit modules each with their own address bus. Does the PPU use them as a combined 32k 16bit or does it make use of the unique address bus to access each with different addresses?

I'm assuming the latter and after a bit of a search I noticed srg320's fpga implementation of the SNES. Line 280+ shows the VRAM treated as a single 32k 16bit ram IF the address for each ram module is the same (low byte in one module and high byte in the other). However, it has a special case for when the VRAM A & B addresses differ and appears to use the previously read value for VRAMB. Which suggests there are times the PPU treats the VRAM as 32k 16bit, but then this other case where it does not.

Anyone familiar with the PPU able to clear up in what cases the two ram modules would be accessed with differing addresses and why in such a case srg320's code returns a previously read temporary value for the B ram data? Or ideally, point me to any resource that covers this part of the PPU?

Author:  dougeff [ Wed Jan 02, 2019 9:47 am ]
Post subject:  Re: PPU dual VRAM addressing

It works as 16 bits per address, 32k of addresses.

Though, if you look at it in a emulator/debugger, it looks like 64k of single bytes.

Author:  nocash [ Wed Jan 02, 2019 10:56 am ]
Post subject:  Re: PPU dual VRAM addressing

Normally, it's just 16bit data with same address for both 8bit chips.
The special case is Mode 7, where it's reading a 8bit BgMap entry and 8bit PixelColor, each from different addresses.
In fullsnes, the info is hiding in this chapter: ... memoryvram

Author:  hicks [ Wed Jan 02, 2019 11:13 am ]
Post subject:  Re: PPU dual VRAM addressing

Thanks for the response and link. I'll get this going without mode 7 support initially and treat it as 32k 16bit VRAM.

Will have to revisit this once I've dug into the PPU and have a better understanding of what mode7 is doing addressing wise to see if I can manage to fit it into the currently limited memory bandwidth.

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