Generate a read signal when accessing 0x8000

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elseyf
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Joined: Sat Dec 01, 2012 4:10 am

Generate a read signal when accessing 0x8000

Post by elseyf » Tue Dec 29, 2020 9:47 am

I have a 74LS139 decoder that is supposed to generate a signal when 0x8000-0xFFFF is read. I use the following setup:

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      74LS139
      ___ ___
     |   v   |
VCC -|1    16|- VCC
    -|2    15|- /RD
    -|3    14|- /CART
    -|4    13|- GND
    -|5    12|- => /RD_CART
    -|6    11|- 
    -|7    10|- 
GND -|8     9|- 
     ---------
Yet somehow the data does not reach the SNES (a black screen occurs).
If I hook up the supposed /RD_CART signal directly to /CART, my setup works, this does however cause a bus conflict if I wanted to write data in the area 0x8000-0xFFFF

nocash
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Re: Generate a read signal when accessing 0x8000

Post by nocash » Tue Dec 29, 2020 11:53 am

That circuit is a bit weird (and it would be easier to read if you had included the pin names from the 74LS139 datasheet).

Basically, you want to OR the /RD and /CART pins? Then why not use an OR gate for that?

Most or all ROMs and EPROMs have two inputs for "ORing" that signals anyways, wire /RD to /OE, and /CART to /CS. Or do you need those pins for other purposes?
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elseyf
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Re: Generate a read signal when accessing 0x8000

Post by elseyf » Tue Dec 29, 2020 12:23 pm

Thanks for the answer.

I will look into it and see if ORing the signals works better.
Meanwhile, I found out that using a 74HC138 does, for whatever reason, work (maybe it's timing related?).

I have a setup where I stream 8-Bit data off a microcontroller to the SNES. It has an output clock that is connected to /RD_CART [= /RD | /CART] together with a buffer IC (74HC245) whose output enable is also connected to that signal. I also want this setup to be able to receive 1-Bit data (through SPI), so that is why I would want separate read and write clocks.

I chose the 74LS139 because that was what I had lying around. It seemed like a good choice, because on the same IC I should have been able to include decoding a write to 0x8000 on the second decoder.

nocash
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Re: Generate a read signal when accessing 0x8000

Post by nocash » Tue Dec 29, 2020 12:47 pm

Yeah, sounds timing related. The /CART signal is derived from some address logic for selecting LoROM and HiROM areas, excluding the WRAM area. That might make /CART a bit slower as when using the raw address bus signals. For the standard LoROM addresses, you could try using /RD=0, A15=1, A22=0 with the 74LS139. Maybe that's a bit faster (when decoding everything in one chip). Or stick with the 74HC139 if that's fast enough.
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