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PostPosted: Tue Oct 18, 2016 9:04 pm 
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I'm developing a game for a subset of the MMC3 that fits on a particular CPLD. I'm trying to ensure that the game doesn't accidentally do anything that the subset can't handle. Is there a way to tell any stable NES emulator to log or stop if any of the following inadvertently occur?

  • Writes to $8000 with a value greater than 7, no matter from which register the write came
  • Writes to $8001 with bit 4 = 1 while $8000 is 0 or 1
  • Writes to $8001 with bit 4 = 0 while $8000 is 2, 3, 4, or 5

The answer to "Then just don't do that!" is "We did not budget for formal verification."

Or would it be better to modify an emulator's source code to support the subset directly?


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PostPosted: Tue Oct 18, 2016 9:06 pm 
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Lua scripting in FCEUX should be able to handle that.

Modifying the emulator source code shouldn't be too hard, either.

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PostPosted: Tue Oct 18, 2016 10:11 pm 
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If you wanted to go NES-code-only, you could track it in your code (and I suppose remove the checks when you're done testing). Since mapper registers generally aren't readable I like to keep a shadow copy in RAM. If you did that, you could use a macro or subroutine for all mapper writes and check for whatever conditions you want by reading those shadow copies. Though I guess that solution falls apart if your code timing is so tight that adding anything will completely break everything.


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PostPosted: Wed Oct 19, 2016 8:00 am 
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Don't forget to set a breakpoint on writes $8002-9FFF to trap possible unintended writes to these as well.

Curious how this is credited.


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PostPosted: Wed Oct 19, 2016 10:37 am 
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Is this like DxROM (mapper 206), or does it have more features/bits?

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PostPosted: Wed Oct 19, 2016 2:34 pm 
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It's sort of like mapper 206 (Namco 108/Tengen MIMIC-1) in lacking mirroring, WRAM, and CP bits, and having a reduced CHR capacity. It's also sort of like 88 in that PPU $0xxx (BG) is always the first half of CHR and PPU $1xxx (sprites) is always the second half. But it has the full MMC3 PIT at $C000-$E001 because levels use lots of parallax splits.

Mapper 88: 128K PRG, 128K CHR (CHR A16 = PPU A12)
Mapper 4: 512K PRG, 256K CHR (all bits switchable), CP, variable mirroring, WRAM, PIT
Our MMC3 subset: 512K PRG, 32K CHR (CHR A14 = PPU A12), PIT


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PostPosted: Wed Oct 19, 2016 3:20 pm 
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"PIT" = programmable interrupt timer, I expect, but "CP bits"?


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PostPosted: Wed Oct 19, 2016 3:30 pm 
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The "CP bits" are [$8000] & $C0 , using the terminology from the wiki (and meaning "Chr" and "Prg" reordering)


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PostPosted: Wed Oct 19, 2016 3:44 pm 
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…Banking modes.


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