Secamline wrote: ↑Sun Aug 16, 2020 8:17 pm
So, the CIRAM/CE pin tells the PPU wether to enable the VRAM (which I just learned was also called CIRAM to add up to the confusion) and/or CHR ROM/RAM, right?
Well, the CIRAM /CE pin enables/disables the internal VRAM, but it doesn't affect the CHR-ROM/RAM on the cartridge. What normally happens is that the cartridge uses the PPU A13 signal to detect whether the PPU is accessing $0000-$1FFF or $2000-$3FFF, and based on that it will enable either the CHR-RAM/ROM on the cartridge or the internal VRAM (via the CIRAM /CE line), but these are separate operations.
So if the VRAM is disabled, the CHR chip provides nametables and palettes ontop of pattern tables?
Yes, if the internal VRAM is disabled and the CHR-ROM/RAM chip is enabled when the PPU is accessing $2000-$3FFF, the PPU will treat the contents of CHR-RAM/ROM as name/attribute data. This is actually one way to implement a 4-screen name table layout in CHR-RAM cartridges: you just disable the CIRAM permanently and leave a 16KB (or more) CHR-RAM chip permanently enabled, causing it to be used for patterns as well as for name/attribute tables (not palettes, though - palettes are always stored inside the PPU itself).
I assume this means that CHR RAM is used instead of CHR ROM.
It works with ROM too, but the types of games you can make exclusively with ROM name tables is very limited!
I guess this also means that CHR RAM is larger than 8K in this case.
Normally yes, but it doesn't have to be. If it's 8KB or less, that simply means that the memory will be mirrored across the PPU address space, and the programmer will be responsible for deciding which tiles to sacrifice so they can be used for name/attributes instead.
Does it mean that addresses $2000 through $3FFF are then mapped to CHR RAM?
Yes.
Also, if CHR ROM/RAM is disabled, where are the pattern tables stored in the PPU's memory map? And what are PPU addresses $0000-$1FFF mapped to?
If you keep the internal VRAM enabled, then that's what will show up at $0000-$1FFF, meaning you'll only have 2KB for all your tiles and name/pattern tables. I don't recall whether there's an iNES mapper number for that configuration, but there are a couple of homebrew games that use the internal VRAM like that... they're sometimes called "single-chip NES games", because they only have the PRG chip (
here's one of those games - scroll down to find the NES version, along with pictures of the "single-chip NES cartridge").
Also could you tell me which chip in the cartridge the CIRAM/CE pin is connected to.
Depends on the cartridge, but the cartridge connector offers both PPU A13 and PPU /A13, so you have both signals readily available to enable/disable any chips you see fit. The "/CE" in the pin's name means that CIRAM is enabled when that line is low, and PPU A13 is high when $2000-$3FFF is accessed, so in most cases you'll probably see PPU /A13 directly connected to CIRAM /CE.
If I were to take a wild guess, I'd say the MMC chip tells the PRG and CHR chips which banks to expose to the CPU and PPU
That is correct. Mappers kinda sit between the CPU/PPU and the memory chips in the cartridge, and the commands they receive from the CPU affect which banks they expose to the CPU/PPU.