i see opcode halt about http://www.devrs.com/gb/files/faqs.html#HALT
There is such a description.
------------------------------------------------------------------------------
HALT operates differently depending on whether the Interrupt Master Enable (IME) is set or reset.
Assembly command EI sets IME to 1.
Assembly command DI resets IME to 0.
IME = 0 - [$ff0f].AND.[$ffff] = 0 :
HALT is aborted. Next instruction is executed normally.
If IME is set to 1 at a later time then a halt condition
will occur one instruction after IME is set to 1 to complete
the halt that was not allowed to finish earlier.
------------------------------------------------------------------------------
If the description is correct... emm..
At IME=0, [$ff0f].AND.[$ffff] = = 0
If DMG executes halt, it will not cause a pause.
In this case, DMG will continue to execute instructions after halt?
halt in IME=0 && IF&IE==0
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Re: halt in IME=0 && IF&IE==0
That's incorrect. The correct behavior of HALT is as follows:
-
If IME == 1:
Execution is paused until IE & IF & $1F != 0 -
If IME == 0:
-
If IE & IF & $1F == 0:
Execution is paused until IE & IF & $1F != 0, after which execution resumes normally.
This is basically the same as IME = 1, but the interrupt handler is not called. -
If IE & IF & $1F != 0:
Execution doesn't pause, but the byte after the HALT is read twice (PC fails to increment).
This would cause single-byte instructions to be simply repeated (such as `dec a`), and multi-byte instructions will read the opcode again as the first operand byte, and the last operand byte will be executed as an opcode. (Example: `ld a, $AF` = `3E AF` will turn into `3E 3E AF` = `ld a, $3E ; xor a`)
-
If IE & IF & $1F == 0:
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