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PostPosted: Fri Jun 28, 2013 7:22 am 
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Attached is a high-level overview of how the PPU chip is laid out (sorry for the large image size). Some of the boxes are bound to be overly specific or general, but it should give the right idea at least.

I'm adding new node names to a repository at https://github.com/ulfalizer/Visual-2C02-nodes while I explore. They can be added to a local version of Visual 2C02 by adding the following line to index.html after the line for nodenames.js:

Code:
<script src="nodenames_extra.js"></script>


The file itself is a bit messy as I had to jump back and forth a lot to figure out what things were, and some things could use shorter, more meaningful names, but it has pretty good coverage at least and should be very helpful for figuring out "random logic" parts of the PPU.


Attachments:
ppuareas.png
ppuareas.png [ 1.77 MiB | Viewed 2002 times ]


Last edited by ulfalizer on Fri Jun 28, 2013 9:12 pm, edited 1 time in total.
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PostPosted: Fri Jun 28, 2013 2:50 pm 
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"Johnson counter". (Yep, that's all I have to contribute to this thread, haha)


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PostPosted: Fri Jun 28, 2013 6:44 pm 
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koitsu wrote:
"Johnson counter". (Yep, that's all I have to contribute to this thread, haha)

For the benefit of others who don't know what it is, a Johnson counter is a type of ring counter which outputs a sequence of 0s followed by a sequence of 1s, which is what the PPU's chroma phase generator (as well as the 2A03's clock divider) happens to use.

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PostPosted: Sat Jun 29, 2013 12:15 pm 
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koitsu wrote:
"Johnson counter". (Yep, that's all I have to contribute to this thread, haha)
Heh, you thought it counts dicks YOU DIRTY BASTARD... ;)


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PostPosted: Mon Jul 01, 2013 10:50 pm 
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"Dot counter" and "Scanline counter" are referred in PPU patent as "H counter" and "V counter" respectively. Or simply "H/V counters" )


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PostPosted: Mon Jul 01, 2013 11:33 pm 
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My version :)

http://breaknes.com/files/PPU/tilemap


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PostPosted: Tue Jul 02, 2013 1:44 am 
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What does the patent call loopy v/t? Haven't looked at it yet.


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PostPosted: Tue Jul 02, 2013 2:42 am 
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Obviously its not "loopy" :))

Registers are named as: tile V.COUNTER, tile H.COUNTER, SCCV (Scroll character V) / VRAM ARL (address register low), SCCH (Scroll Character H) / VRAM ARH (address register high).
And Picture Address Register (PAR) as aggregate register.

Although I prefer to call it TV, TH (tile scroll) and FV, FH (fine scroll).


Attachments:
2C02_patent.jpg
2C02_patent.jpg [ 176.25 KiB | Viewed 1730 times ]
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PostPosted: Tue Jul 02, 2013 3:53 am 
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Bleh, I'll always suck at reading box-and-line diagrams. :P

I think I'll stick to coarse/fine x/y and t/v, as that's the terminology people are most used to. I added a link to your annotations to the Visual Circuit Tutorial, as it's more detailed and it's nice to have a double take on things. :)


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PostPosted: Tue Jul 02, 2013 4:33 am 
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Quote:
I added a link to your annotations to the Visual Circuit Tutorial
Great, this link will be permanent )


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