MMC3/IRQ Question

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oRBIT2002
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MMC3/IRQ Question

Post by oRBIT2002 » Sun Mar 19, 2006 3:47 am

There's been alot of talk that the IRQ counter decreases when the "A12 on the PPU bus toggles from 0-1".
What does this mean in plain english? Does it mean when bit 12 of the PPU address switches from 0 to 1 when for example setting an address via $2006?
It only decreases on toggle? Assuming the previous bit 12 was 1, and writing another 1 on bit 12 won't decrease the counter?

Another question about $A001 register. It seems pretty simple but what's the point of disabling WRAM or make it readable/writable only? Is this feature actually used in games and if so, why? :)

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hap
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Re: MMC3/IRQ Question

Post by hap » Sun Mar 19, 2006 4:38 am

oRBIT2002 wrote:Does it mean when bit 12 of the PPU address switches from 0 to 1 when for example setting an address via $2006?
It only decreases on toggle? Assuming the previous bit 12 was 1, and writing another 1 on bit 12 won't decrease the counter?
You got it right. You'll need a pretty solid PPU emulator though, before MMC3 games will look right with the correct implementation. Before that, you're better off with a hackish hblank counter.

The use of disabling WRAM is probably to prevent accidental WRAM corruption, and it could also possibly be used to prevent piracy. Remember a message like "Please hold the reset button when turning off the console" in old SRAM games like Final Fantasy 1 ?

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oRBIT2002
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Post by oRBIT2002 » Sun Mar 19, 2006 4:42 am

Thanks for your reply! Most mapper-documentation today is alot more detailed than when I previously read them a few years ago, but they are not always that easy to understand if you're not highly skilled in eletronics. :)

Oh of course, I remember seeing that message on Zelda2 and on more recent versions of Zelda 1 aswell, even if they did have MMC1.

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oRBIT2002
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Post by oRBIT2002 » Sun Mar 19, 2006 5:12 am

I just thought of something else.. The counter is affected aswell when the PPU Address is auto-incremented when $2007 is written to?

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blargg
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Post by blargg » Sun Mar 19, 2006 5:20 am

Yes, the counter is incremented no matter what the cause of the A12 line going from low to high (0 to 1). I've tested using auto-incrementing when reading $2007. Note that it somehow filters out the multiple transitions of A12 that occur during PPU rendering on each scanline (and not due to the 22 pf capacitor across the A12 line either, since I tried removing that once).

darklink
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Post by darklink » Sat May 20, 2006 12:01 pm

so, is there any commerce game that do toggle the A12 line to trigger an irq?
English is NOT my mother language.
And my English is poor.
So please, don't be crazy on me when you have a hard reading,
and welcome for you to point out my error.
Thanks !

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blargg
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Post by blargg » Sat May 20, 2006 12:22 pm

is there any commerce game that do toggle the A12 line to trigger an irq?
The way to test this in an emulator is to "mark" the IRQ counter whenever the A12 line is toggled from 0 to 1 via PPU register writes, then log an occurrence if this marked counter value causes an IRQ. Anything which resets the counter would "unmark" it.

darklink
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Post by darklink » Sat May 20, 2006 1:18 pm

No, I just want to know if any game make use of toggling that lines to generate an IRQ for some reason ?
if not, then treat it as an accurate rendered-scanline counter is ok.
English is NOT my mother language.
And my English is poor.
So please, don't be crazy on me when you have a hard reading,
and welcome for you to point out my error.
Thanks !

tepples
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Post by tepples » Sat May 20, 2006 8:07 pm

Kick Master depends on accurate IRQ handling at several points, such as the end of level 2.

darklink
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Post by darklink » Sun May 21, 2006 6:14 pm

thank blarggs and tepples

I will use it to test when implemente MMC3 IRQ.
English is NOT my mother language.
And my English is poor.
So please, don't be crazy on me when you have a hard reading,
and welcome for you to point out my error.
Thanks !

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