NMI Hijacking IRQ

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Anes
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NMI Hijacking IRQ

Post by Anes » Wed May 20, 2015 8:48 am

I have been trying to pass Blargg's cpu interrupts test.
My question is about NMI hijacking an IRQ. Is the NMI flip-flop cleared when the CPU is on an IRQ sequence and jumps to the NMI vector??

What i did was simple, i have a flag -> "on_irq" and at the beggining of my runcpu() fn it checks if this flag is set, if it is set my emu calls an IRQ() fn that does cycle by cycle what IRQ does and in the 6th and 7th checks if my other flag "nmi_pending" is set and lad PCL and PCH with NMI vectors respectivly.

I ask if it clears the NMI flip-flop, becouse if it doesn't it would jump NMI vector (since i check NMI at the beggining of my code too)

The thing i cannot pass the NMI hijacking an IRQ test.
ANes

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Zepper
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Re: NMI Hijacking IRQ

Post by Zepper » Wed May 20, 2015 2:22 pm

Before the 2 last cycles of IRQ (code below), check for a pending NMI and fetch the appropriate vector. Yes, clear the pending NMI.

Code: Select all

#define INT_IRQ() \
   readvalue(cpu->PC); \
   readvalue(cpu->PC); \
   PUSH(cpu->PC >> 8); cpu->S--; \
   PUSH(cpu->PC); cpu->S--; \
   PUSH(cpu->P & 0xEF); cpu->S--; \
   cpu->P |= I_BIT; \
   if(nmitrig) { \
      cpu->PC  = readvalue(NMI_VEC); \
      cpu->PC |= readvalue(NMI_VECH) << 8; \
      nmi_request = 0; \
   } else { \
      cpu->PC  = readvalue(IRQ_VEC); \
      cpu->PC |= readvalue(IRQ_VECH) << 8; \
   }

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Anes
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Re: NMI Hijacking IRQ

Post by Anes » Thu May 21, 2015 2:52 pm

mmm... i'm still getting errors. Could be the clock jitter?? It's working bad. It throws me error #5 "odd not working propertly".
I have read this post about you and Blargg talking about this topic viewtopic.php?t=3926
Quoting Blarrg he says:
You aren't handling odd clock jitter properly. It's really simple, if the APU is on an odd clock on the $4017 write, act as if the write was one clock later.
I don't understand what he means with "one clock later". Is the APU clock the CPU cc counter??

Im doing this too:

- Is the sequencer divider reset to "0" when $4017 is written??
- Is the current sequence set to "0" i mean the next sequence will be the first after writing to $4017??

is it wrong?
ANes

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Zepper
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Re: NMI Hijacking IRQ

Post by Zepper » Thu May 21, 2015 6:18 pm

Quote from somewhere... :)

Code: Select all

        When writing to $4017, the frame counter reset 
        and the quarter/half frame triggers happen simultaneously,
        but only on "odd" cycles (and only after the first "even" cycle
        after the write occurs) - thus, it happens either 2 or 3 cycles
        after the write (i.e. on the 2nd or 3rd cycle of the next instruction).
        After 2 or 3 clock cycles (depending on when the write is performed),
        the timer is reset.
        If the mode flag is set, then both "quarter frame" and "half frame"
        signals are also generated. 

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Re: NMI Hijacking IRQ

Post by tepples » Thu May 21, 2015 7:21 pm

Another way of expressing it:
Everything in the APU is clocked at half the CPU clock rate, except for the triangle wave's period divider.

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Re: NMI Hijacking IRQ

Post by Anes » Thu May 21, 2015 8:46 pm

tepples wrote:Another way of expressing it:
Everything in the APU is clocked at half the CPU clock rate, except for the triangle wave's period divider.
Tha'ts my problem i read that and i tried to clock my prog timers (pulse1, pulse2, nosie, DMC) every OTHER cc (as the wiki says) but it sounds bad. I'm currently clocking those progtimers with each cpu cc. For example if the instrutctions takes 3 cc the timers are (if the are not 0) decremented thrice. But the way im implementing it gives me at least a "NES like" sound.

if i clock every OTHER cc is the timers are divided by two, thus decrementing the freq.

I'll keep trying...
ANes

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Re: NMI Hijacking IRQ

Post by Zepper » Fri May 22, 2015 5:53 am

tepples wrote:Another way of expressing it:
Everything in the APU is clocked at half the CPU clock rate, except for the triangle wave's period divider.
This is a technical detail that messed up the things. All my APU emulation is/was fine with 29830 CPU cycles, including running test ROMs... and one day, _Q said "no, it's the half of that".

In short words, there's NO problem of keeping the old fashioned way of clocking the APU/counting cycles, Anes.

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Re: NMI Hijacking IRQ

Post by x0000 » Fri May 22, 2015 6:39 am

tepples wrote:Another way of expressing it:
Everything in the APU is clocked at half the CPU clock rate, except for the triangle wave's period divider.
LFSR is clocked on every second CPU tick, thats all that matters.

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Re: NMI Hijacking IRQ

Post by Anes » Fri May 22, 2015 6:56 pm

Zepper wrote:In short words, there's NO problem of keeping the old fashioned way of clocking the APU/counting cycles, Anes.
Well, that gives me a beacon of light in my emu dev Zepper...
ANes

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