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PostPosted: Sat Nov 16, 2013 4:40 am 
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Joined: Fri Jul 19, 2013 11:38 am
Posts: 115
I'm halfway-ish done making my PPU cycle-specific, but I'm still wondering when the CPU needs to let the PPU cycle 3 times. Basically, what I have right now, is that the PPU's tick() method (basically just calls cycle() 3x) is called in:

- CPU's memory.read method
- CPU's memory.write method
- Whenever an additional cycle is required when branching/page crossing

Now, I have implemented dummy memory.reads to get that extra cycle in 1-byte operations, which makes sense. The things that confuse me are instructions like Zero Page ASL (OP $06) because they require 5 cycles, and here is what I might be misunderstanding (or not):

- Cycle 1: Fetching OP from PC (check)
- Cycle 2: Fetching zero page address from PC + 1 (check)
- Cycle 3: Fetching data from zero page address (check)
- Cycle 4: Writing altered data back to memory (check)
- Cycle 5: ??????? (not check)

Now, if I had to guess, this 5th cycle would actually be the 4th cycle (so between the above mentioned cycle 3 and 4), and basically this cycle is where all the shifting and flag checking would happen. If that's the case, then my (Java) code looks something like this:

Code:
public void executeInstruction() {
    int op = memory.read(PC++); //CPU cycles once, PPU cycles 3 times
..... //something something something
    switch(op) {
.....
    case 0x06: //ASL with zero page addressing
        asl(getZeroAddress());
        break;
.....
}

.....
.....
.....

public void asl(int address) {
    int data = memory.read(address); //CPU cycles once, PPU cycles 3 times
    data <<= 1;
    checkCarry(data);
    checkZero(data);
    checkSign(data);
    data &= 0xFF;
    ppu.tick(); //CPU cycled once, let the PPU cycle 3 times
    memory.write(address, data); //CPU cycles once, PPU cycles 3 times
}
.....
.....
.....
public int getZeroAddress() {
    return memory.read(PC++); //CPU cycles once, PPU cycles 3 times
}


Is this correct, or am I misunderstanding something?


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PostPosted: Sat Nov 16, 2013 8:48 am 
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Joined: Fri Jul 19, 2013 11:38 am
Posts: 115
Never mind.

There's a very handy document (http://users.telenet.be/kim1-6502/6502/hwman.html#AA) which describes exactly for which operations in combination with certain addressing modes a dummy read/write happens (appendix A). In the case of ASL, a dummy write happens after the data is read, i.e. the same data which is read is written back to memory without alteration.

Just for the people who didn't know (doubtful, but still).

Anyway, this still leaves me with a question, if I may put it in the same thread which is only partially related:

The aforementioned document (appendix A, page 4, section 2.5) speaks of this:

"Carry is 0 or 1 as required from previous add operation"

What does this imply? I get that for some operations, when a page boundary is crossed, a previous read will be discarded as faulty, and a new read will be done, making the discarded read effectively a dummy read. The thing I just don't get is what the carry has to do with it. Can anyone answer this for me?


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PostPosted: Sat Nov 16, 2013 11:45 am 
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Joined: Mon Sep 27, 2004 8:33 am
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Location: Central Texas, USA
The 6502's 8-bit adder has a carry output for multi-byte operations. The address calculation logic examines this after adding the low byte and index register to determine whether a page crossing occurred and it needs to increment the high byte and redo the access.


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PostPosted: Sat Nov 16, 2013 2:52 pm 
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Joined: Fri Jul 19, 2013 11:38 am
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blargg wrote:
The 6502's 8-bit adder has a carry output for multi-byte operations. The address calculation logic examines this after adding the low byte and index register to determine whether a page crossing occurred and it needs to increment the high byte and redo the access.


Ah, so we're not talking about the same carry as in the 6502's processor status register. Good to know, I was confused as to what the heck the carry flag had anything to do with this operation. Thanks.


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PostPosted: Sat Nov 16, 2013 4:50 pm 
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Location: Central Texas, USA
Yeah, the entities in the bus-level description are typically not visible at the architectural level (e.g. ADH, ADL).


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PostPosted: Sat Nov 16, 2013 5:25 pm 
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Joined: Fri Jul 19, 2013 11:38 am
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I suppose so. I haven't seen these things before in any other 6502 documentation. It's nice to know though, because that information made my CPU core a step closer to the real deal ^^


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