Becoming an FPGA Engineer

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tepples
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Re: Becoming an FPGA Engineer

Post by tepples »

In Furrtek's decap and trace of the MMC3 (GitHub; previous discussion), M2 delay appears to be done by passing the signal through a bunch of buffer gates used for their gate delay. Your FPGA may or may not support a corresponding design idiom.
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krzysiobal
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Re: Becoming an FPGA Engineer

Post by krzysiobal »

Instead of trying non synthetisable command like "delay", try searching if your FPGA have built in feature for programmable delay.
For example - the cheap popular EPM240 has and it can be turned as follows:
pd.png
BTW. The signal initial value assignment is not synthetisable in al chips, you should use dedicated reset or for example - first rising edge of M2 should initialize it.
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Ben Boldt
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Re: Becoming an FPGA Engineer

Post by Ben Boldt »

krzysiobal wrote: Wed Jun 09, 2021 1:48 pm Instead of trying non synthetisable command like "delay", try searching if your FPGA have built in feature for programmable delay.
For example - the cheap popular EPM240 has and it can be turned as follows:
pd.png

BTW. The signal initial value assignment is not synthetisable in al chips, you should use dedicated reset or for example - first rising edge of M2 should initialize it.
I think this chip does have exactly the delay type you are talking about. I am having trouble figuring out how the heck to use that though and not sure I can specify how long for the delay. Anyway, it unassigns my M2 pin whenever I try, and even automatically assigned it to some other dedicated clock input type pin. Not really sure what all happened there, maybe I clicked something I didn't realize. It looks promising though. I believe this demo board has 10MHz clock already available on pin H5, I will see if I can use it for a counter style delay. I think it will be a simpler challenge at my low experience level.

I have a question about your suggestion using the first rising edge of M2 to initialize everything. How can I keep track that it was the first rising edge? I think I will need a flag initialized clear that can be set after the first rising edge. How could I initialize that flag itself?


Edit:
I was able to tap into that 10 MHz demo board clock signal:

tek00022.png

But now I am thinking, that signal has a period of 100 nsec. That is probably too coarse for this delay, especially since it will be asynchronous to M2. And judging by the rise and fall times, it doesn't look like I can go much faster than that. Admittedly, this is an output signal in the scope shot and not the actual input signal but just generally ballpark speaking, I don't think going 10x to a 100MHz signal looks like a great idea at least with this particular chip.

Creating a low-pass of M2 (i.e. a hardware delay) and feeding it to another pin might not be a bad idea. Man this stuff is so interesting, all new problems I have never dealt with before.


Edit 2:

You know what, I had my scope's bandwidth limit turned on. Here it is without (full 500 MHz limit):

tek00023.png
Trirosmos
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Re: Becoming an FPGA Engineer

Post by Trirosmos »

Ben Boldt wrote: Wed Jun 09, 2021 4:02 pm
krzysiobal wrote: Wed Jun 09, 2021 1:48 pm Instead of trying non synthetisable command like "delay", try searching if your FPGA have built in feature for programmable delay.
For example - the cheap popular EPM240 has and it can be turned as follows:
pd.png

BTW. The signal initial value assignment is not synthetisable in al chips, you should use dedicated reset or for example - first rising edge of M2 should initialize it.
I think this chip does have exactly the delay type you are talking about. I am having trouble figuring out how the heck to use that though and not sure I can specify how long for the delay. Anyway, it unassigns my M2 pin whenever I try, and even automatically assigned it to some other dedicated clock input type pin. Not really sure what all happened there, maybe I clicked something I didn't realize. It looks promising though.
I'm doubtful that this option would give enough of a delay for this application. Maybe low-passing M2 like the mapper lidnariq posted about could work?
Alternatively, if your RAM is slow enough, I suppose having short false positives on the RAM /CE and RAM /WE lines wouldn't matter?
Ben Boldt wrote: Wed Jun 09, 2021 4:02 pm But now I am thinking, that signal has a period of 100 nsec. That is probably too coarse for this delay, especially since it will be asynchronous to M2.
Maybe you could trigger your M2 buffer on both edges of that signal? But even without that, if you're feeding M2 into a 2-bit shift register and clocking said register at 10 MHz, wouldn't the worst-case delay be 200 ns total? Even with glacially slow 70 ns memory, that should still be plenty of time before the falling edge of M2.
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