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PostPosted: Tue Oct 01, 2013 2:26 pm 
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I found a MMC3 clone (labeled 88), thanks to MWK from famicomworld. The same thing happens.


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PostPosted: Mon Oct 14, 2013 9:30 pm 
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any updates on this I've highly curious.


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PostPosted: Wed Oct 16, 2013 3:57 am 
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I am very busy and I don't have time to test it on a real hardware
but I will work on it whenever I have some free time
So please be patient :wink:


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PostPosted: Sun Nov 03, 2013 4:26 am 
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very interesting the freeze of Ninja Gaiden III is caused by an unwanted clock signal generation during the game play and it happens whenever you want to go back :
02:9903:2C E6 6F BIT $6FE6

So as a result one TTL (174) is not enough for this cartridge and it needs a 238
Mapper schematic will be very similar to 8 IN 1 SLROM Multicartridge

But why does CPU access to this area($6FE6)? :shock:


Last edited by FARID on Sun Nov 03, 2013 9:28 am, edited 2 times in total.

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PostPosted: Sun Nov 03, 2013 5:55 am 
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If i can find a 238 i will try it.
PS: Also ng1 and ng2 seems to freeze, but more rare. Usully it freeze when you turn back a few screens.


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PostPosted: Sun Nov 03, 2013 7:20 am 
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FARID wrote:
But why does CPU access to this area($6FE6)? :shock:

Seems like a leftover read with no real purpose, you should be able to overwrite it with NOPs.

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PostPosted: Sun Nov 03, 2013 12:14 pm 
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You shouldn't need the additional 74'138 for the protection. You should be able to just use a 74'161, with its /CLEAR, ↑LATCH, and /LATCHENABLE inputs.

Connect CPU D4..D7 to 161 D0..D3, connect Q0 and Q1 to PRG/CHR A17/A18, connect Q3 to /LATCHENABLE. /CLEAR and ↑LATCH are unchanged. I think you don't even need to change any of Farid's code, although you'll need to reorder the PRG banks or use the Ninja-Shadow-less version.

On the other hand, it's also utterly trivial to NOP out the BIT instruction — it's immediately followed by LDA #0 so I can't imagine it has any effect.


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PostPosted: Mon Nov 04, 2013 12:28 am 
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Thanks lidnariq, your idea is really awesome :D

Registers :
[D7-- --D0]
[ABCD EFGH]
A --> D7 --> x
B --> D6 --> x
C --> D5 --> x
D --> D4 --> x
E --> D3 --> x
F --> D2 --> LATCH [0:EN 1:DIS]
G --> D1 --> PRG A18 + CHR A18
H --> D0 --> PRG A17 + CHR A17

ROM1 --> Ninja Gaiden III --> 1100 1100 --> CC [MENU]
ROM2 --> Ninja Gaiden II ---> 1110 1110 --> EE
ROM3 --> Ninja Gaiden I ----> 1111 1111 --> FF

Image


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PostPosted: Mon Nov 04, 2013 12:02 pm 
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It's working! It's working!
Thank you Farid and Lidnariq!
Tested on a mmc3 and usa nes2.


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PostPosted: Tue Nov 17, 2015 6:20 am 
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Does anyone have a picture of the result? I'm curious how it looks. Thanks again.


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PostPosted: Wed Mar 02, 2016 4:27 am 
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FARID can you post source code for menu from first post, please :) ?


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PostPosted: Thu Mar 03, 2016 11:08 am 
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soulstorm wrote:
FARID can you post source code for menu from first post, please :) ?


You can use this : MMC3 and MMC1 Menu for Famicom TXROM PCB reproduction


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PostPosted: Fri Mar 04, 2016 12:50 am 
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Thanks! But I want to make simple multicart for 4 games by using 2 x AT29C040 and 74HC174 as Latch.
No any CHR-RAM stuff needed. Also I can't understand how to make host game not first in game list.


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PostPosted: Fri Mar 04, 2016 4:37 pm 
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Am I missing something important here?

I applied the correct patches to the correct ROMs, however, only ninja Gaiden 3 runs from the menu.


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PostPosted: Sun Mar 06, 2016 9:48 pm 
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On emulator or real hardware?

Is the ROM structure correct?
header
PRG2
PRG1
PRG3
PRG4
CHR1
CHR2
CHR3
CHR4


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