It is currently Sun Feb 18, 2018 11:23 pm

All times are UTC - 7 hours





Post new topic Reply to topic  [ 6 posts ] 
Author Message
 Post subject: Boot timing
PostPosted: Wed Apr 13, 2016 12:52 pm 
Offline

Joined: Tue Oct 20, 2015 2:25 am
Posts: 24
While designing my MMC3 clone, I have noticed CPLDs have a relatively high configuration time (for a 128 macrocell density one, it's about 400 us). So I was wondering if they will be fast enough to be operative when the console starts requesting data...

So the question is... how much time do I have since power is applied to the cartridge port, to the moment at which the CPU and PPU start reading data from the ROMs?


Top
 Profile  
 
 Post subject: Re: Boot timing
PostPosted: Wed Apr 13, 2016 4:31 pm 
Offline

Joined: Sun Apr 13, 2008 11:12 am
Posts: 6777
Location: Seattle
In my experience, the voltages stabilize close to 0.1 seconds before the CPU is released from reset... but you really should double check. (I've only got my two NES-CPU-07 boards to test with)


Top
 Profile  
 
 Post subject: Re: Boot timing
PostPosted: Wed Apr 13, 2016 4:54 pm 
Offline

Joined: Sun Jun 12, 2011 12:06 pm
Posts: 300
Location: Poland
What CPLD are you talking about?
I built my flash-cart on XC9572 (which emulates MMC1/UNROM/CNROM/NROM) and I have absolutelly no issues, this CPLD is instantly ready after powerup, because the cell data is stored internally. I have got problems that you describe with FPGA, because the cells information is stored in external flash and after powerup, the ram has to be read and then transferred to FPGA.


Top
 Profile  
 
 Post subject: Re: Boot timing
PostPosted: Wed Apr 13, 2016 4:57 pm 
Offline

Joined: Sun Sep 19, 2004 11:12 pm
Posts: 19635
Location: NE Indiana, USA (NTSC)
Would the CPU come out of reset sooner on a Famicom or NES-101?

Does your CPLD's datasheet state that all pins are high-Z (not connected) until configuration completes? If so, you may be able to work around this by using resistors to create a fixed bank. This way, the CPU can at least spin for a few milliseconds while the CPLD boots.


Top
 Profile  
 
 Post subject: Re: Boot timing
PostPosted: Thu Apr 14, 2016 1:15 am 
Offline

Joined: Tue Oct 20, 2015 2:25 am
Posts: 24
@krzysiobal I have checked so far 2 CPLDs:
- Xilinx XC2C128: 350 us configuration time (from datasheet).
- Lattice LCMXO256C: I have not found the exact number. Family datasheet states it "boots in microseconds", but I haven't found how many. Wake from sleep timing for this CPLD is 400 us, so I assume configuration time might be similar (maybe a bit bigger).

@tepples Inputs are high impedance. I already thought about that, but I want to avoid it unless really needed.

Doesn't anybody have measurements? How is the NES internal reset circuitry? RC based maybe?


Top
 Profile  
 
 Post subject: Re: Boot timing
PostPosted: Thu Apr 14, 2016 1:22 am 
Offline

Joined: Tue Oct 20, 2015 2:25 am
Posts: 24
lidnariq wrote:
In my experience, the voltages stabilize close to 0.1 seconds before the CPU is released from reset... but you really should double check. (I've only got my two NES-CPU-07 boards to test with)

Didn't see this post. If the value is correct, 0.1 s should be a lot more than enough, thanks!


Top
 Profile  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic  [ 6 posts ] 

All times are UTC - 7 hours


Who is online

Users browsing this forum: Google [Bot], Google Feedfetcher and 8 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
Powered by phpBB® Forum Software © phpBB Group