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PostPosted: Sun Dec 25, 2016 9:13 am 
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Location: Poland
I think there is something wrong with description of this chip that is published on the internet OR i have other version of this chip.
This chip is from some famiclone game (probably some kind of Quattro - Arcade/Adventure or so). I did complete PCB rev-en of this cardridge:
Image Image

So, what are my observations:
1. CPU_!ROMSEL and CPU_R/!W lines are reversed
2. PRG_A16 and PRG_A17 are reversed.

More over, in all Quattro NES roms player on emulator (FCEUX): Adventure, Sports, Arcade when you choose second game from the menu, in facts third game is launched and when you chose third - second is launched. This might be the cause that author of emulator implemented mapper 232 according to the bad specification that is over internet.

Another more technical aspect that I have discovered is that the BF9096 chip is clocked by all of these three lines: CPU-!ROMSEL, CPU-R/!W, CPU-A14 (or rather internally by signal generated by oring all of them?) - so if all of these lines are at 0 and any of them goes to 1, the mapper latches to PRG-A16/PRG-A17 the vaue of D4/D3.


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PostPosted: Sun Dec 25, 2016 11:23 am 
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Joined: Sun Apr 13, 2008 11:12 am
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Location: UK (temporarily)
krzysiobal wrote:
2. PRG_A16 and PRG_A17 are reversed.
[...]
More over, in all Quattro NES roms player on emulator (FCEUX): Adventure, Sports, Arcade when you choose second game from the menu, in facts third game is launched and when you chose third - second is launched.
Does it seem more likely that the dump is wrong, or that the bits in the register are out of order?
e.g. on the wiki we say
Code:
  $8000-BFFF:   [...B B...]   PRG Block Select
but if those two bits are actually D4→A16 and D3→A17 then this is a documentation issue, rather than a dump issue.

Quote:
Another more technical aspect that I have discovered is that the BF9096 chip is clocked by all of these three lines: CPU-!ROMSEL, CPU-R/!W, CPU-A14 (or rather internally by signal generated by oring all of them?)
That feels like the simplest way to do that, and safe given the timing of the 2A03


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PostPosted: Mon Dec 26, 2016 6:09 am 
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Joined: Sun Jun 12, 2011 12:06 pm
Posts: 245
Location: Poland
Here is proof of the latching timings:
Image

Next interesting thing in this chip is pin 16. According to documentation it is GND, but after desoldering and measuring resistance on diode test there is about 600 mV drop between pin 10 (GND1) and pin16 (GND2), so this might be some kind of controlling or testing pin. Unfortunatelly according to my observation, this chip behaves the same if pin 16 is pulled to GND or VCC>

And the CIC output pin is de facto M2 divided by 2 (M2 is not used for anything else).
Image


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PostPosted: Tue Dec 27, 2016 4:37 pm 
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Location: UK (temporarily)
What software did you find/buy/write to explore the state machine of the BF9096?


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PostPosted: Tue Dec 27, 2016 5:05 pm 
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Joined: Sun Jun 12, 2011 12:06 pm
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It is a device + program made by my hands.
Image Image Image

The device consists of DIL ZIF socket and Atmega 8 which communicate with PC through USB. 30 out of 32 pins (except bottom left and top right) are connected with Atmega pins (with serial resistors). Atemga can read/write signals on any of those pins. Serial resistors protect pins from overcurrent if there is different logic level on both sides.

The PC part is a control program written in C#. It basically allows doing following things:
* reading ROMs/EPROM/Flash
* programming flash
* automatic testing IC circuits (74xx, SRAMs, asics, pals, etc). The logic function of such device is hardcoded in PC application, so adding new device is just matter of minutes - add new class defining logic of outputs with respect to inputs.
* dumping PALs.

I succesfully restored PALS of 168-in-1 famiclone multicart, golden 5 (5-in-1) famiclone multicart.

Few days ago I aded useful function for manipulating the logic levels of pins just by clicking on them so it can be used for fast testing behaviour of some new chips.

Image Image Image


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