FDS DRAM controller
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Author:  lidnariq [ Sun Oct 09, 2016 7:07 pm ]
Post subject:  FDS DRAM controller

Does anyone have an FDS and an oscilloscope or logic analyzer? I'm curious about several completely unimportant aspects of its DRAM controller.

Things like:
/RAS-only refresh? or /CAS-before-/RAS refresh? or Hidden refresh? (or NO refresh??)
How do CPU A0-A14 map through the multiplexers?
What selects between the two /CAS lines?

Author:  koitsu [ Sun Oct 09, 2016 9:03 pm ]
Post subject:  Re: FDS DRAM controller

I have both (FDS and access to a scope, no logic analyser). I'm not familiar with how to wire/hook up what you want to be tested, however, so I'm probably not a good candidate. Maybe Dead_Body?

Author:  lidnariq [ Sun Oct 09, 2016 9:54 pm ]
Post subject:  Re: FDS DRAM controller

Given 'scope probes on /RAS and /CAS0:

/RAS-only refresh:
/RAS ¯¯¯___¯¯¯
/CAS ¯¯¯¯¯¯¯¯¯
/CAS-before-/RAS refresh:
/RAS ¯¯¯¯¯¯___¯¯¯
/CAS ¯¯¯______¯¯¯
Hidden refresh:
/RAS ¯¯¯______¯¯¯___¯¯¯
/CAS ¯¯¯¯¯¯_________¯¯¯
A normal read/write cycle:
/RAS ¯¯¯______¯¯¯
/CAS ¯¯¯¯¯¯___¯¯¯

The other questions require active hunting, unfortunately. I assume one of the CPU address lines directly controls which of the two /CAS lines is asserted, (i.e. /CAS0 would stay high when Axx was high, for some unknown xx)

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