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PostPosted: Thu Mar 15, 2018 11:21 am 
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When during it's read cycle does the PPU sample the data bus? On the rising edge of /RD?


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PostPosted: Thu Mar 15, 2018 8:38 pm 
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Oops. I pretty much already asked this question in one of my other threads. Sorry!

Still, if anyone can answer or tell me how to figure it out on Visual2C02, that would be helpful.
I'm not sure what signal(s) I should be looking at in Visual2C02 during the read cycle to know when the data bus is sampled.


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PostPosted: Thu Mar 15, 2018 9:04 pm 
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Unfortunately, it depends on which read cycle. (CPU-initiated or ordinary PPU cadence?)

The signal comes from the pin ( "_db0") and then goes into through a series of inverters and/or transmission gates.

The multiplexed AD0 pin continuously drives _db0 internally.

For ... I think both nametable and pattern table fetches, _db0 is inverted by t13021 into node 8755; a transmission gate (t13047) then allows that signal to flow into node 8739 when pclk1is high.
That signal is then inverted by t13030 into node 8770; and that then goes through several more inverters and transmission gates.

For pattern table fetches, _db0 instead goes through transmission gate t13136 or t13954 depending on horizontal flip status, before going through another transmission gate (t13188 or t14039 respectively) while pclk1 is high.

pclk1 seems to be high for the second half of each pixel.

In contrast, for CPU-initiated reads, data instead flows through transmission gate t15845, and this territory is a little too complex and uncharted for me to care enough to figure out the rest.


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PostPosted: Fri Mar 16, 2018 5:51 pm 
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So, there is an input node that is basically an active-high latch, with pclk1 being the latch enable.

At Visual2C02, I can see that the /RD line goes active (low) for a total of 8 half-cycles of the master clock.
pclk1 is high for the last four of these half-cycles (as you, lidnariq, said), so the latching is active during this time.
Therefore a memory device has until pclk1 goes low (minus some propagation delay/setup time) to write to the memory bus.

Does this sound correct?

Thanks a lot, lidnariq, for your answer and for telling me about pclk1. Very helpful!


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PostPosted: Fri Mar 16, 2018 6:24 pm 
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It's a little weird to call a transmission gate an active-high latch, but ... sure, why not.

Your grasp of what's going on matches mine, which ... I wouldn't claim is particularly great but there you go.


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