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Following a conversion on the wiki talk page, I have transcribed and translated the Japanese VRC6 data sheet, hopefully without introducing critical errors. I had understood modes 0 to 2 well enough, but was confused about mirroring in mode 3, and the point of clearing the Mode Register's bit 5.

The data sheet made it reasonably clear to me that Mode Register bit 5 being cleared is supposed to be used with 512 KiB (4 kilobit) of CHR-ROM, and that the CHR-ROM must be connected differently. The data sheet does not specify how exactly, but connecting VRC6's A10-A17 to CHR-ROM's A11-A18 and PPU's A10 to CHR-ROM's A10 seems to be the only plausible way, and then the behavior of Mode 1 with bit 5 cleared makes perfect sense: use the same eight bank data bits unchanged for the upper and lower 1 KiB part of the 2 KiB CHR bank as CHR A11-A18, and use PPU A10 as CHR A10, yielding 256 2 KiB banks for a total of 512 KiB.

I still have not the slightest clue about how Mode 3's mirroring really works, and more importantly: what is the point of that complicated nonsense? What application does it have? The data sheet does not provide an explanation, only four examples that are not helpful at all.

Attached Nintendulator source file is written to succeed at Natt's test ROMs. But those (to my knowledge, correct me if I'm wrong) have never been tried on real hardware, and my combinatorial logic of the mirroring behavior in the source file is just me trying to turn the lookup tables from the wiki into something that can be expressed without tables. Also, I tried to implement how I think the 512 KiB CHR-ROM mode works without having any opportunity to test it.

(@rainwarrior: I spotted and corrected some mistakes compared to the previous version of the transcript.)

Edit: v0.2, correcting a typo in a number.

Mode 3 allows generating four nametables while only using 2 control registers, by having the "CHR A10 override" be on the other axis from the mirroring specified by CR6/CR7 layout.

It's ... uh, "clever", but on the existing VRC6 PCBs only useful with ROM nametables.

Ah, I didn't understand this from the tables that were on the wiki, but going by the document it seems like "mode 3" is 2k nametable banking, rather than 1k.

($B003 & F) = 3
"Vertical" spread of 2k banks


($B003 & F) = 7
"Horizontal" spread of 2k banks


($B003 & F) = B
Limited "vertical mirroring" of 1k banks (only odds accessible)


($B003 & F) = F
Limited "horizontal mirroring" of 1k banks (only evens accessible)


Is this correct?(If yes, I think the tables need to have separate columns for 2 and 3 instead of combining them, even though technically the same registers are used for control, the expression is different because it's 2k instead of 1k?

The existing tables were trying to explain the full functionality, including undefined behavior, especially when bit 5 was clear. But I agree it's confusing and obscures why you'd care.

(I don't think the CHR bank table should have four columns. I could see the argument that the Nametable bank and Mirroring tables should be somehow combined)

The CHR tables are fine, this difference only applies to nametables and mirroring.

...but also now that I know about this I can suddenly see that for the mirroring table, the nametable registers ALWAYS apply. (Except for mode 0 where it subsitutes PPU 10/11?) This is what I was most confused about, I thought the A10 signal was passing PPU A10 through when in CIRAM mode, but it's really just being forced by that even odd logic?

As far as I can tell, there are the following "well defined" modes:

$20 - standard 8x1 banking, only intended to work with 2 KiB of NTRAM, but the upper address lines still do something funny during nametable fetches
$21 - standard 4x2 banking, arbitrary nametable layouts with access to two up-to-256 K memories
$22 - N108 style banking, for picking arbitrary source nametables but only in 1/H/V configurations
$23 - N108 style banking, for generating 4 nametables
$01 - 4x2 banking, 512K CHR, arbitrary nametable layouts, but only half of each CHR bank available for ROM nametables.

The other three – $00, $02, and $03 – are artifacts of how the logic works, and what I was trying to express with the weird tables.

In practice, you could probably say "there are 32 ways to configure [$B003] & $1F, but nametable behavior falls out into the following 11 behaviors:

00 06 07 08 0E 0F 26 2E - all have horizontal mirroring with R6/R7 controlling the specific source nametables
01 05 09 0D 21 25 29 2D - all have arbitrary mirroring with R4-R7 controlling
02 03 04 0A 0B 0C 22 2A - all have vertical mirroring with R6/R7 controlling the specific source nametables

ROM nametables hard to use and 8x1 banking:
20 - vertical mirroring (or horizontal spread of ROM nametables, but R6/R7 is used to both specify a nametable and pattern table bank, so hard to use)
24 - horizontal mirroring (or vertical spread, &c)
28 - 1scA
2C - 1scB
ROM nametables easy to use and N108 CHR banking:
23 - horizontal mirroring, or vertical spread of 4 ROM nametables
27 - vertical mirroring, or horizontal spread of 4 ROM nametables
2B - 1scB - I don't know why you'd bother
2F - 1scA - I don't know why you'd bother "

Right. PPU A10 is only what's used on pattern table addresses.

As far as I know, someone did run them on a VRC6 cart: https://forums.nesdev.com/viewtopic.php ... 55#p138055

The "4 mode" structure of the document I think made it clear to me how the mirroring was supposed to work.

I applied this to the document by splittng the Mirroring section with 4 similar tables:
https://wiki.nesdev.com/w/index.php/VRC6#Mirroring

My remaining questions are:

1. What does mode 0 + ROM nametables do? (Not officially documented.) I would guess that CHR A10 is exactly the same as when using CIRAM, but the upper 7 bits of the registers still apply as per the nametable register table?

2. What happens with bit 5 clear? (Again undocumented.) I think the answer to this is probably on the table here somewhere, but I'm still trying to piece it together. It sounds like the nametable register LSB always goes to CHR A10, but how do I describe the effect of this... Though I suppose it being an undocumented and unsupported mode, not intended for this kind of wiring anyway, maybe just a 16 column table would be fine.

Correct. If I haven't confused myself, it works out to be transposed version of the mode 3 + ROM nametables layouts.

When bit 5 is clear, the eight latches are just used verbatim, and nothing replaces CHR A10 ever. With 12 slots and eight registers, that means that the same number appears several times. For modes $02/$03 that's not too bad—CR0 CR1 CR2 CR3 CR4 CR4 CR5 CR5 CR6 CR7 CR6 CR7—but still silly in comparison to using mode $22. For mode $04 it's equally useful—CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR6 CR7 CR6 CR7—there's still two slots that hold a uselessly duplicated value, but now the duplicated values are also being displayed as a nametable.

Hm, seems like my emulation source may well represent instead of merely replicate the chip's actual behavior, as the inverted axis is represented by the B003_MIRRORING ^(B003_CHR_MODE &1) [after restricting to B003_CHR_MODE ==0 || B003_CHR_MODE ==3). The interesting part would be to make a test ROM, and in a pipe dream, a custom test PCB, for the 512 KiB CHR mode.
Ah, good.

That's what I concluded as well, following the same logic.

It seems really curious to me that mode 3 is a transposed version of this, like they just didn't realize they'd accidentally implemented this mapping twice. (Or maybe they're deliberately reusing it, just in an order they liked better, hence the two kinda weird single screen modes.)

Anyhow, I think I've covered the whole thing on the wiki now... I hope it's not too much information, but it's at least all in tables and hierarchically organized. Conveniently the "important" mode is mode 0 anyway, which comes first and has the shortest description.

Nice. On a different note, I find it funny that Konami calls the PPU "VDP" in the document.