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PostPosted: Mon Mar 12, 2018 5:41 am 
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Location: NE Indiana, USA (NTSC)
The VRC7 needs 42 cycles of delay after a write to $9030. The simpler Famicom expansion audio chips probably do not. In "VRC6 audio delay after write?", it was concluded that someone at Konami probably forgot to remove the delays when porting Akumajou Densetsu from something else (possibly VRC7) to VRC6.

Like the VRC7, the Namco 163 uses a round-robin approach to synthesis and mixing, visiting one voice every 15 CPU cycles. Has rapid-fire access to N163 audio RAM been tested?


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PostPosted: Mon Mar 12, 2018 6:03 pm 
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Joined: Sun Jan 22, 2012 12:03 pm
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Location: Canada
Well, sample fill loops routinely write to it at a pretty rapid pace. Also like with VRC6 we have Famitracker and PPMCK/MML engines which have both been working fine on hardware without any explicit delay code. Similarly I've never noticed anything my hotswap tests.

There doesn't seem to be any synchronization conflicts (e.g. writing to a sample or frequency that is currently being played), but there's no known interface to query/control the current state of that 15 clock cycle either, so any such conflict would probably be impossible to avoid if they existed.

So... there's no suspected speed limit on my part, I only asked about VRC6 because of that weird looking code in AD.


For me, there's some unknowns about how the sample phase is stored (can sort of "read" it as sample data through audio output, and may be able to just read it back out through the data port, but I haven't attempted this yet). 0 to all 3 phase bytes does appear to reset phase.

Other than that, I don't really have any leads on anything I think is worth testing at this point. If there's something specific you have in mind, please write up a hotswap ROM and I can try it out for you.


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