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PostPosted: Sun Dec 31, 2017 6:10 pm 
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Well, awhile back I bought this very strange board off of ebay. It's a clone of Vs. SMB. This in and of itself isn't terribly interesting. What is, is that it does not use the conventional CPU/PPU combo! No sir, they recreated the CPU and PPU functionality in TTL logic! There's a stock 6502 now vs. the RP2A03, and the PPU is made up mainly of TTL logic with a small PLD thrown in and a few PALs for the X and Y counting.

It appears to have been designed some time around 1986 when Vs. SMB came out. The chip dates are from 1985 and 1986. The NES audio is done with a Z80 *emulating* the APU registers, and uses two SN76489's. This sounds as amusing as you can imagine it does. The quality of the emulation is very poor and hilarious, but I think it could've been done much better. Pitch sweeps are mainly what's totally hosed. You can hear this in the youtube video (below).

Tile rendering is done very similar to how a real PPU performs it, just with all TTL logic. X scrolling is implemented, but Y scroll isn't. Sprite 0 hit is not implemented either, and goes off after the 4th tile row is rendered, which is used to split the screen for the status/score bar in the game. They even implemented the same attribute system.

Sprites are a giant lol and extremely interesting- They use frame buffers! There's two 256*256 pixel frame buffers. One is loaded with sprites while the other is being displayed. It takes the hardware two scanlines to load a single sprite into the buffer, and they seem to load one every 4 scanlines, so it takes 256 scanlines to render all 64 sprites to the buffer. This means sprites lag tiles 1 frame but this isn't terribly noticeable.

Timing is pretty far off from a real system. It runs at 16MHz and divides this by 3 to get a 5.33MHz pixel clock which is really close to the native 5.36MHz. There's 336 cycles per scanline and 280 scanlines per frame, which gives around a 56Hz frame rate. The CPU runs at 2MHz. Of course this isn't a big deal for this particular game.

When the 6502 writes to an audio register address (4000-400f, 4010-4015 are not implemented) it halts the 6502, the Z80 reads which address and the data written, then starts the 6502 back up. This way it does not miss multiple consecutive audio writes. Also related, sprite DMA is not implemented, and the game as to bang out data into 2004 manually. This might be why vblank is extended so much (18 extra vblank lines).

That's about it, I have produced a complete schematic of the PCB and a video showing the board running and a detailed look at how it works on the schematic. Enjoy!

youtube video:

https://youtu.be/g8gZT1F9UkE

schematic:

http://blog.kevtris.org/blogfiles/vssmbbootleg.PDF

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PostPosted: Sun Dec 31, 2017 6:52 pm 
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great!

you have mapper 127 dd2 Rom?


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PostPosted: Mon Jan 01, 2018 7:50 pm 
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A very cool and amusing analysis. Can you guess why they took such a convoluted route? Ineptitude? Sheer brilliance and willpower? Cost savings?

I wonder why a lot of the bootleg systems out of the far east try to duplicate successful tile-based hardware by using framebuffer-based displays.... do you have any idea?

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PostPosted: Mon Jan 01, 2018 9:11 pm 
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ccovell wrote:
A very cool and amusing analysis. Can you guess why they took such a convoluted route? Ineptitude? Sheer brilliance and willpower? Cost savings?

I wonder why a lot of the bootleg systems out of the far east try to duplicate successful tile-based hardware by using framebuffer-based displays.... do you have any idea?


I'm clueless. I really want to know too. It appears to have been designed in 1986 and made in late 86. Latest chip date was 8630, so about mid-1986. Of course it was probably made later than this, but I am guessing the end of '86. I believe they wanted to clone the game since they figured it was going to be really hot in the arcades. They must've had fun reverse engineering the CPU/PPU, and since they are custom parts figured they could reproduce it with off the shelf stuff. And that is what they did. I am wondering if they were anticipating using the same or similar hardware to clone other vs. games or not. Sprite 0 hits are hard coded for the status bar split and there's no Y scrolling. The Y scroll could've been added fairly easily though. The circuit does seem optimized somewhat for vs. SMB.

Well the tile hardware technically wasn't turned into a frame buffer, only sprites. But I am guessing it is because frame buffers are fairly easy to make and require relatively light hardware so they just go with path of least resistance. I am also curious where this was designed. The PCB has no markings on it to speak of (no board number, no maker) and the ROMs don't have any indicating marks in them either. There was plenty of empty space to doodle on, like 16K worth of ROM in that sprite ROM.

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