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PostPosted: Sat May 11, 2019 1:15 pm 
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from this topic where a glitch is discussed, and a hardware mod is given as a solution

Quote:
put a 1nF capacitor on the leg of pin 20 (CE) (note: actually /CE) of the PRG ram chip and connect the other to ground


what purpose does this serve? is there a name for this piece of the circuit? how does the value of the cap affect things?


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PostPosted: Sat May 11, 2019 2:20 pm 
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It'll delay reads from and writes to RAM by a little bit. If there's a glitch because /ROMSEL arrives later than M2, and that glitch causes an erroneous write to RAM when the game tries to set the IRQ, then the capacitor might help with that.

Slower RAMs should also work.


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PostPosted: Sat May 11, 2019 4:10 pm 
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lidnariq wrote:
It'll delay reads from and writes to RAM by a little bit. If there's a glitch because /ROMSEL arrives later than M2, and that glitch causes an erroneous write to RAM when the game tries to set the IRQ, then the capacitor might help with that.

Slower RAMs should also work.


I wonder why the NES decided to leave as many pins for "expansion" as they did, without feeding A15 or the 6000-7FFF decode signal to the cartridge port, since either of those would have eliminated the need for the timing cap.


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PostPosted: Sat May 11, 2019 4:31 pm 
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They didn't really reevaluate what they were doing after the Famicom; they just stuck an extra 10 pins on to subsume the FDS cable, and another 4 for the CIC.

There's lots of little things that seem obvious in hindsight that would have either saved money or simplified certain things afterwards. Adding A15, adding inverted M2, adding inverted R/W, connecting some of the unused GPIO (OUT{1,2}; 401{6,7}d{1,2}) all would helped with cost reduction, without any silicon die changes at all.


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PostPosted: Sun May 12, 2019 10:59 am 
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lidnariq wrote:
They didn't really reevaluate what they were doing after the Famicom; they just stuck an extra 10 pins on to subsume the FDS cable, and another 4 for the CIC.

There's lots of little things that seem obvious in hindsight that would have either saved money or simplified certain things afterwards. Adding A15, adding inverted M2, adding inverted R/W, connecting some of the unused GPIO (OUT{1,2}; 401{6,7}d{1,2}) all would helped with cost reduction, without any silicon die changes at all.


I'm not sure why inverted M2 or inverted R/W would be generated in the console. A15 is generated internally and used to derive other signals, including decodes for address ranges $0000-$1FFF and $2000-$3FFF, and the chip which generates those also generates signals for the $4000-$5FFF and $6000-$7FFF blocks. Although there are some places where adding chips in the console could have save cost in some cartridges, the signals mentioned already exist in the console.

BTW, I'm curious how the PPU memory layout evolved, since it seems needlessly complex from both a hardware and software standpoint. A 2Kx8 chip would have enough storage to store a screen worth of tiles, each with a separate attribute byte, and 16x8, 8x16, or ignore-attributes modes could have accommodated games that need double buffering. I wonder if the intention was to make the chip usable with a pair of 1Kx4 static RAMs?


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PostPosted: Sun May 12, 2019 12:54 pm 
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supercat wrote:
I'm not sure why inverted M2
A lot of 74 parts use an active-low enable.
Quote:
or inverted R/W
Obviates the need for bus conflict prevention.

The NES already has a 74HCU04 to generate the clock for the CIC, and the other five are enlisted in CIC clock distribution (to prevent the cartridge for being able to short out the CIC clock), PPU /A13 generation, audio amplifier, and LED driver. I'm pretty certain that at least one inverter could be repurposed without compromising those functions.

Quote:
BTW, I'm curious how the PPU memory layout evolved, since it seems needlessly complex from both a hardware and software standpoint.
Are you already familiar with the TMS9918? (MSX, SG1000). Beyond things like raster timing, its memory layout also influenced the NES PPU.... oh you're talking specifically about the attribute table.

Quote:
16x8, 8x16, or ignore-attributes modes
Non-square attribute zones would probably have been deemed too much of a pain to use - at least, that's what I heard when people more skilled with pixel art were told that we could give them finer attribute zones. No-attribute mode probably would have been nixed for being insufficiently colorful.
Quote:
could have accommodated games that need double buffering.
I can guarantee that they never even considered double buffering as a use case. I'm comfortable saying that porting all of Nintendo's existing arcade games, as of 1983, was a design parameter for the PPU, and that includes smooth scrolling (e.g. Sky Skipper). But double buffering in 1983 was just too expensive for something where other options look good enough.
Quote:
I wonder if the intention was to make the chip usable with a pair of 1Kx4 static RAMs?
They clearly bent over backwards to fit into 1KiB, but I'm a little skeptical that they ever specifically aimed at having only 1KiB of RAM for the PPU.


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PostPosted: Thu May 16, 2019 6:36 am 
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Don't put a capacitor between /CE and GND. From my experience it is very problematic, for example - for -70ns SRAMs it worked, for -200ns it produced hanging of WRAM-based games randomly. Also it depended on the consoles, on some model it worked and on some doesn't.
Better use the diode-resistor-capacitor delay circuit on the RAM/CE pin.


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PostPosted: Sat May 18, 2019 11:14 am 
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krzysiobal wrote:
Don't put a capacitor between /CE and GND. From my experience it is very problematic, for example - for -70ns SRAMs it worked, for -200ns it produced hanging of WRAM-based games randomly. Also it depended on the consoles, on some model it worked and on some doesn't.
Better use the diode-resistor-capacitor delay circuit on the RAM/CE pin.


do you have some info on that circuit you can point me to?


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PostPosted: Sat May 18, 2019 11:43 am 
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Code:
/RAMCE --+--|>|--+-- RAM /CE
         |       |
         +---R---+
                 |
                 C
                 |
                gnd
The important difference is that just adding the capacitor delays the end of the RAM I/O condition also, but adding the diode pulls the signal up quickly when the RAM I/O condition ends.
Exact time constant for RC should be on the order of 30-50ns, maybe C=22pF and R=2.2k


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