A hypothetical MMC3-like mapper without a CPLD

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A hypothetical MMC3-like mapper without a CPLD

Post by Joe » Fri May 07, 2021 12:49 pm

Reading about mapper design had me wondering just what it would take to build something like the MMC3 using only new DIP ICs.

Turns out it's pretty easy once you have a GAL16V8.

PRG and CHR bank registers can be handled by a bunch of 74*670s. A single *670 can give you four 8KB PRG banks out of a 128KB PRG ROM, or four 2K banks of a 32KB CHR ROM (or RAM). A pair can handle either 2MB of PRG or 512KB of CHR.

The *670 has three-state outputs, so some extra logic in the 16V8 can disable its outputs at some addresses and rely on pull-up resistors to create a fixed bank. If this replaces all of the highest bank, it frees up one bank register for PRG RAM at $6000-$7FFF.

One bit of each of the CHR registers can be stolen to control name table mirroring, reducing the maximum CHR size to 16KB with a single *670 or 256KB with a pair. If you've been working out how to wire this up, you might have noticed that pattern table banking would use PPU A12 and A11, but name table banking would need PPU A11 and A10. The 16V8 can solve this problem by generating (A12 AND NOT A13) OR (A10 AND A13) to control one of the *670 read address lines. (I considered four-screen mirroring instead, but then it wouldn't be compatible with the famiclones that rely on the connection between PPU /A13 and CIRAM /CE.)

Now for the fun part: the scanline counter.
irq.png (11.08 KiB) Viewed 3605 times
Okay, you got me, this is actually more like Acclaim's MC-ACC instead of Nintendo's MMC3. Much like the MC-ACC scanline counter, this one depends on background patterns at $0000, sprite patterns at $1000, and 8x8 sprites. It probably also needs a glitch filter on PPU A12.

Programming it would involve writing one register to enable/acknowledge/reload the counter, and writing another register to disable and acknowledge the counter. Keeping the IRQ disabled after the write requires internal feedback in the 16V8, which seems like it would work okay:

Code: Select all

**** CUPL: ****
load = romsel & write & a14 & a13;
clear = (clear & !(romsel & write & a14 & a13)) # (romsel & write & a14 & !a13);

**** Compiled equations (according to jedutil): ****
/o12 = /i1 & /i2 & i3 & i4
o12.oe = vcc

/o13 = i1 & /o13 +
       i2 & /o13 +
       /i3 & /o13 +
       /i4 & /o13 +
       /i1 & /i2 & i3 & /i4
o13.oe = vcc
Okay, let's see how many 16V8 outputs that uses...
  • PRG bank *670 /WR
  • CHR bank *670 /WR
  • PRG bank *670 /RD
  • CHR bank *670 address line
  • scanline counter /MR
  • scanline counter /PL
One output left. I guess we can throw in PRG ROM /CE and get rid of bus conflicts. These would be the required inputs:
  • R/W
  • CPU A14
  • CPU A13
  • M2
  • PPU A13
  • PPU A12
  • PPU A10
Two inputs left. If you add another CPU address line, you can move the registers out of the way and have self-flashing too.

Now all I have to do is build it... and then write a game that uses it...

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Re: A hypothetical MMC3-like mapper without a CPLD

Post by calima » Fri May 07, 2021 10:50 pm

Is this just for fun, or do you expect it to be significantly cheaper than the current mmc3 boards?

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Re: A hypothetical MMC3-like mapper without a CPLD

Post by lidnariq » Fri May 07, 2021 11:01 pm

Definitely not cheaper. 74'670s are tragically expensive now.

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Re: A hypothetical MMC3-like mapper without a CPLD

Post by Joe » Sat May 08, 2021 1:40 am

This is just for fun. You wouldn't build this thing if you're worried about how much it costs.

Although, you could replace the four 74*670 with eight 74*373 (or 74*573), a couple of 74*139, and... two 74*04, I think? Spend the money you save on cheaper parts to get a bigger board to hold all of them.

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Re: A hypothetical MMC3-like mapper without a CPLD

Post by krzysiobal » Sat May 08, 2021 7:08 am

Feel free to beat the record of number in chips used. The current recold holder is: viewtopic.php?f=9&t=16123

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