After desoldering it I was able to deduct which pin is GND and which is +5V. Among the NC pins I found PRG-A18 and PRG-/A17 (and so the D4 data pin that countrols it).
Code: Select all
Irem's TAM-S1 IC
.---v---.
N/C PRG A18 <- |01 28| <- CPU A14 n
r PRG A16 <- |02 27| -> PRG A17 r
r PRG A15 <- |03 26| -> PRG A14 r
rn PPU A10 -- |04 25| -> PRG /A17 N/C
rn PPU A11 -> |05 24| -> CIRAM A10 n
GND prgce mode -> |06 23| <- ? N/C
GND GND -- |07 22| <- ? N/C
N/C xor a14 -> |08 21| -- +5V +5V
n R/W -> |09 20| <- PRG /CE r
GND data in -> |10 19| <- CPU /ROMSEL n
N/C data out <- |11 18| <- CPU D7 rn
rn CPU D0 -> |12 17| <- CPU D5 +5V
rn CPU D1 -> |13 16| <- CPU D4 GND
rn CPU D2 -> |14 15| <- CPU D3 rn
'-------'
^---how the chip is wired on Kaiketsu Yanchamaru PCB---^
----------------------------------------------------------------------------------------------------------
PRG-ROM is DIP32 but with weird pinout
*32, 31, 30 = VCC
*24 = A16
*1 = A17
others seem to follow JEDEC
----------------------------------------------------------------------------------------------------------
[M.XPPPPP]
| ||||||
| |+++++-- PRG bank
| +------- controls how pin 11 behaves
| 0:pin 11 follows pin 10
| 1:pin 11 is high impedance
+--------- mirroring (1=V, 0=H)
pin 8 = 0: REG at $c000 (mask = $c000), $8000=PPPPP, $c000=-1
pin 8 = 1: REG at $8000 (mask = $c000), $8000=-1, $c000=PPPPP
Writes appear to take place on rising edge of /ROMSEL when R/W is low.
----------------------------------------------------------------------------------------------------------
P06 P08 R/W /RS P22 P23 A14 || PRG/CE
1 * 1 * * * * 1
0 * * 1 * * * 1
0 * 1 0 * * * 0
0 0 0 0 * * 0 0
0 0 0 0 * * 1 1
0 1 0 0 * * 0 1
0 1 0 0 * * 1 0
1 0 0 * 1 0 0 0
1 0 0 * 1 0 1 1
1 1 0 * 1 0 0 1
1 1 0 * 1 0 1 0
1 * 0 * 0 0 * 0
1 * 0 * * 1 * 1
As you can see, even in the default configuration (P06=0, P08=N/C=1),
PRG/CE is asserted during writes to $c000-$ffff
----------------------------------------------------------------------------------------------------------
Wiki says that there are two bits controlling mirroring, but CPU-D6 is not routed to the chip at all.
And even trying to apply different combinations of other data pins does not seem to switch to single
screen mirroring.