Irem's TAM-S1 IC analysis

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krzysiobal
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Irem's TAM-S1 IC analysis

Post by krzysiobal »

I'm checking the TAM-S1 chip. Apparently, `Kaiketsu Yanchamaru` (256kB PRG / 8kB CHR-RAM) is the only game that uses it. Mapper 97 is extremelly simple, but this 28 pin mapper chip seems to be connected in extraweird way - lot of not connected pins, multpiple +5Vs/GNDs.

After desoldering it I was able to deduct which pin is GND and which is +5V. Among the NC pins I found PRG-A18 and PRG-/A17 (and so the D4 data pin that countrols it).

Code: Select all

                      Irem's TAM-S1 IC
                         .---v---.
 N/C          PRG A18 <- |01   28| <- CPU A14          n
 r            PRG A16 <- |02   27| -> PRG A17          r       
 r            PRG A15 <- |03   26| -> PRG A14          r
 rn           PPU A10 -- |04   25| -> PRG /A17         N/C
 rn           PPU A11 -> |05   24| -> CIRAM A10        n
 GND       prgce mode -> |06   23| <- ?                N/C
 GND              GND -- |07   22| <- ?                N/C
 N/C          xor a14 -> |08   21| -- +5V              +5V
 n                R/W -> |09   20| <- PRG /CE          r
 GND          data in -> |10   19| <- CPU /ROMSEL      n
 N/C         data out <- |11   18| <- CPU D7           rn
 rn            CPU D0 -> |12   17| <- CPU D5           +5V
 rn            CPU D1 -> |13   16| <- CPU D4           GND
 rn            CPU D2 -> |14   15| <- CPU D3           rn
                         '-------'                      
 ^---how the chip is wired on Kaiketsu Yanchamaru PCB---^

----------------------------------------------------------------------------------------------------------

PRG-ROM is DIP32 but with weird pinout
*32, 31, 30 = VCC
*24 = A16
*1 = A17
others seem to follow JEDEC

----------------------------------------------------------------------------------------------------------

[M.XPPPPP]
 | ||||||                                            
 | |+++++-- PRG bank 
 | +------- controls how pin 11 behaves              
 |           0:pin 11 follows pin 10
 |           1:pin 11 is high impedance              
 +--------- mirroring (1=V, 0=H)                     
 
pin 8 = 0: REG at $c000 (mask = $c000), $8000=PPPPP, $c000=-1
pin 8 = 1: REG at $8000 (mask = $c000), $8000=-1,    $c000=PPPPP
   
Writes appear to take place on rising edge of /ROMSEL when R/W is low.

----------------------------------------------------------------------------------------------------------

P06 P08 R/W /RS P22 P23 A14 || PRG/CE
 1   *   1   *   *   *   *        1
 0   *   *   1   *   *   *        1
 0   *   1   0   *   *   *        0
 
 0   0   0   0   *   *   0        0
 0   0   0   0   *   *   1        1
 0   1   0   0   *   *   0        1
 0   1   0   0   *   *   1        0

 1   0   0   *   1   0   0        0
 1   0   0   *   1   0   1        1
 1   1   0   *   1   0   0        1
 1   1   0   *   1   0   1        0
 1   *   0   *   0   0   *        0
 1   *   0   *   *   1   *        1
 
 
 As you can see, even in the default configuration (P06=0, P08=N/C=1),
 PRG/CE is asserted during writes to $c000-$ffff
 
----------------------------------------------------------------------------------------------------------

Wiki says that there are two bits controlling mirroring, but CPU-D6 is not routed to the chip at all.
And even trying to apply different combinations of other data pins does not seem to switch to single
screen mirroring.
lidnariq
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Re: Irem's TAM-S1 IC analysis

Post by lidnariq »

... so in conclusion, it does have bus conflicts, for absolutely no good reason?

I spent a few minutes trying to figure out if there was an obvious way to rewire pins 6,8,9,19,22,23,28 to do anything else useful at all, but I don't see anything...

Also looks like pin 11 could be coaxed into providing another bit of PRG banking by adding an external pullup resistor. But I can't figure out what else it could possibly be useful for.
Last edited by lidnariq on Wed Feb 19, 2020 12:43 pm, edited 1 time in total.
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krzysiobal
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Re: Irem's TAM-S1 IC analysis

Post by krzysiobal »

lidnariq wrote: Wed Feb 19, 2020 11:51 am ... so in conclusion, it does have bus conflicts, for absolutely no good reason?
In the first half of PRG space (where the register is located) - no bus conflicts. But the other one suffers from bus conflicts.
Don't see good reason what's the point of enablin ROM there. Maybe the line can be reused to control additional RAM and pins 22/23 can be CPU-A13/CPU-A14? Or the chip was meant to be used for other consoles/computer with different memory organisation.
Also looks like pin 11 could be coaxed into providing another bit of PRG banking by adding an external pullup resistor. But I can't figure out what else it could possibly be useful for.
Cascade it with ciram-a10 and add third mirroring mode: one-screen
lidnariq
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Re: Irem's TAM-S1 IC analysis

Post by lidnariq »

krzysiobal wrote: Wed Feb 19, 2020 12:40 pm Don't see good reason what's the point of enabling ROM there. Maybe the line can be reused to control additional RAM and pins 22/23 can be CPU-A13/CPU-A14?
Now that you mention it, it is fairly reminiscent of the UNROM512 memory map, where there's a 16KB window to access the banking register, and a 16KB window to access the flash's programming interface. Maybe they specified that the mapper IC should make it possible to program a battery-backed RAM in-system.

Do any pins other than 8, 9, 19, 20, and 28 affect where the mapper register is?

There's a subtle almost-symmetry in your table that makes me think that pins 9 and 19 aren't always intended to be R/W and /ROMSEL.

Cascade it with ciram-a10 and add third mirroring mode: one-screen
Hm. In that case, why did you guess that pin 17 was D5 and not D6?

Too bad that the everything is pin 8 XOR pin 28. If one connected CPU A13 to pin 8, it'd produce a memory map of 8+16F+8 which has no advantage over 16F+16. If it were instead XNOR, it would generate the vaguely-useful memory layout of 8F+16+8F.
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krzysiobal
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Re: Irem's TAM-S1 IC analysis

Post by krzysiobal »

Hm. In that case, why did you guess that pin 17 was D5 and not D6?
Can be D6 aswell or even any address bit :)
Because the current mapper definition assigns D6 and D7 to mirroring control and this bit without additional wires does not have influence to mirroring, I prefered to not use it.
lidnariq
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Re: Irem's TAM-S1 IC analysis

Post by lidnariq »

krzysiobal wrote: Thu Feb 20, 2020 9:31 am Because the current mapper definition assigns D6 and D7 to mirroring control and this bit without additional wires does not have influence to mirroring, I preferred to not use it.
That's a good reason.

Unrelatedly, do any pins other than 8, 9, 19, 20, and 28 affect where the mapper register is?

I wrote a program to search for interesting ways to connect all the pins, but right now it's so under-constrained as to be useless.
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Re: Irem's TAM-S1 IC analysis

Post by krzysiobal »

I checked if there seems to be other registers, by issuing a write of different value at the second bank address, also reading with different values of Pin22/23 and it does not affect the currently described functionality - everything seems to be the same (PRG banking, mirroring, data in/data out pin)

What I found new is that when Pin6=1, then for some combinations of Pin22/Pin23 (for example Pin22=any, Pin23=1) writes to register does not have any effect (with pin6=0 the same combination of other pins would allow write). That could be a hint if there might be any other hidden register but I don't know what could it be responsible because there are no unused outputs.

I think the data out pin might be used for interrupts (data in = carry output of external counter, data out = /IRQ) - HiZ mode would be "disable interrupts" and transparent mode would be "enable". But that still would need additional logic for clear/set counter.
lidnariq
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Re: Irem's TAM-S1 IC analysis

Post by lidnariq »

krzysiobal wrote: Thu Feb 20, 2020 6:54 pm I checked if there seems to be other registers, by issuing a write of different value at the second bank address, also reading with different values of Pin22/23 and it does not affect the currently described functionality - everything seems to be the same (PRG banking, mirroring, data in/data out pin)
That's also interesting.

Are PRGA14...PRGA18 just the latched value OR (pin 8 XOR pin 28) ?
What I found new is that when Pin6=1, then for some combinations of Pin22/Pin23 (for example Pin22=any, Pin23=1) writes to register does not have any effect (with pin6=0 the same combination of other pins would allow write).
There's this subtle symmetry in the function table, where pin6=0 means one set of pins are used, and pin6=1 means a different set of pins are used. Maybe. When I converted your lookup table to a function, I saw something that looks like:

Pin6 = 0 means Pin19 disables ROM, otherwise Pin 9 enables ROM, otherwise Pin 8 XOR Pin 28 disable ROM.
Pin6 = 1 means Pin9 or Pin23 disables ROM, otherwise Not-Pin22 enables ROM, otherwise Pin 8 XOR Pin 28 disable ROM.

Assuming I haven't made an error in transcription. Perfectly possible.

So I think your initial guess about "some different CPU control signals convention" is probably right, but what could that possibly be? Nothing I can think of seems quite right.

My only guess is that the full function table for latching will only latch when (pin 8 XOR pin 28) is what disables the ROM, but you also found that it was a rising edge of pin 19 when pin6=0 that causes the value to be stored, and I don't have any guess what the condition would be for pin6=1.
That could be a hint if there might be any other hidden register but I don't know what could it be responsible because there are no unused outputs.
Yeah, I don't suspect multiple registers. I was just wondering if some configuration would move the existing registers to some other address—especially if it would help me narrow down what other permutations could be valid.
HiZ mode would be "disable interrupts" and transparent mode would be "enable".
Is it an active buffer, or is it a transmission gate? If it's the latter, it might be usable as a software mute. (No idea why one'd want that, though...)
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Re: Irem's TAM-S1 IC analysis

Post by krzysiobal »

Are PRGA14...PRGA18 just the latched value OR (pin 8 XOR pin 28)
Yes
what disables the ROM, but you also found that it was a rising edge of pin 19 when pin6=0
No, no.. I just wanted to point that latching occurs on edge, not on level.
On the rising edge of pin 19 chip checks for proper values of other inputs to deremine if latching should be done or not.

So I think your initial guess about "some different CPU control signals convention" is probably right, but what could that possibly be? Nothing I can think of seems quite right.
Don't you think that in this PIN6=1 mode, the function of PRG/CE pin should no longer be considered as rom enable? If it does not even take /ROMSEL into account then it would cause conflicts with RAM, PPU.
It also can't be also used as CHR/CE because it is always 1 when CPU reads..
Is it an active buffer, or is it a transmission gate? If it's the latter, it might be usable as a software mute. (No idea why one'd want that, though...)
In transparent mode, It only outputs 5V/0V, but the rising/falling edges on ouput are really steep and there is almost no delay between input/output suggesting that this is pure buffer, nothing more complicated underneath.
Image Image Image

I might try to make dynamic current consumption analysis like Ben Bolt did to MMC5 when trying to figure out how much bits there are in each register.
lidnariq
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Re: Irem's TAM-S1 IC analysis

Post by lidnariq »

krzysiobal wrote: Fri Feb 21, 2020 6:38 pm No, no.. I just wanted to point that latching occurs on edge, not on level.
On the rising edge of pin 19 chip checks for proper values of other inputs to determine if latching should be done or not.
Right, but is it specifically a rising edge of pin 19 (/ROMSEL)? Or just anything ending the write condition? As far as I know, one write condition is:
Pin6 low and Pin 19 (/ROMSEL) low AND pin 9 (R/W) low AND (pin 8 XOR pin 28) high.

So a rising edge of pin 19 will end the write condition. Will a rising edge of pin 9? Pin 28? Falling edge of pin 8? In other words, are the other signals part of the equation that generates the clock to the register, or does the register have a clock enable?

As far as I know, that's the only valid write condition when pin 6 is low.
Don't you think that in this PIN6=1 mode, the function of PRG/CE pin should no longer be considered as rom enable? If it does not even take /ROMSEL into account then it would cause conflicts with RAM, PPU.
It also can't be also used as CHR/CE because it is always 1 when CPU reads..
Yes, I agree. Because pin6=1 ignores the contents of pin19, pin6=1 requires a different PCB and maybe a different CPU.

Given that pin19 is ignored when pin6=1 for driving PRG/CE low, I assume it's also ignored for latching the register.
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Re: Irem's TAM-S1 IC analysis

Post by krzysiobal »

lidnariq wrote: Fri Feb 21, 2020 7:01 pm So a rising edge of pin 19 will end the write condition. Will a rising edge of pin 9? Pin 28? Falling edge of pin 8? In other words, are the other signals part of the equation that generates the clock to the register, or does the register have a clock enable?
Only rising edge of pin 19 makes write effect. If other pins break the condition, write won't be done (by toggling CPU-A14 you can see what value is stored in register)
Image
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Re: Irem's TAM-S1 IC analysis

Post by lidnariq »

Thanks for clearing that up.

Now I just wonder where the register is when pin6=1. My guess is rising edge of pin 9 or pin 23... although I guess it could still be pin 19, even though it's otherwise unused.

Right now, pin6=1 really looks like pin22 = "/READ" in the same way that pin6=0 has pin9=R/W. But I don't know what to think of pins 9 and 23 in pin6=1 mode.
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