Did some initial poking around in visual2C02, what I saw was ... strange.
tile_l appeared as $00ff during pre-render, and ROR'd starting at dot 76, ROR'ing one bit at a time until it's value was $f807. The next clock was not $fc03 as you'd expect, it was instead $ff03. tile_h appears to follow a similar pattern, but delayed by about 6 dots.
The condensed version of this behavior (intermediate cycles removed, each line represents a single dot) is:
Code: Select all
h v t_l t_h
04b 105 00ff ffff
04c 105 807f ffff
04d 105 c03f ffff
04e 105 e01f ffff
04f 105 f00f ffff
050 105 f807 ffff
051 105 ff03 00ff
052 105 ff81 807f
053 105 ffc0 c03f
054 105 ffe0 e01f
055 105 fff0 f00f
056 105 fff8 f807
057 105 fffc fc03
058 105 fffe fe01
EDIT: Both high and low tiles fetches were $ff from the chr-rom area.
EDIT: After more poking around, I got a single tuple access pattern, I was correct about it not being clocked at dot 0. I was however wrong about them being left shift.
Code: Select all
h v t_l t_h t_buf
000 000 aaaa aaaa aa
001 000 aaaa aaaa aa
002 000 d555 5555 aa
003 000 eaaa 2aaa aa
004 000 f555 1555 aa
005 000 faaa 0aaa aa
006 000 fd55 0555 aa
007 000 feaa 02aa aa
008 000 ff55 0155 aa
009 000 aaaa aaaa aa
Note about the above, t_h is inverted, so I un-inverted it for clarity. Clocks begin at the beginning on dot 2, with data being clocked in on dot 9.