Turned out it was a matter of the free running RC OSC needing to be lower; Increased my R to 10M and C to 370pF got the Xtal circuit running in the 16 MHz range
My values aren't optimized; just happy it's running.
Weird. The original frequency was already just 7kHz, I'm surprised dropping it to 40Hz helped things (as opposed to, say, simply reducing the strength of the bias resistor). Or maybe the extra capacitive load did something. That large of a capacitance should definitely drop the effective frequency of the crystal, though. (How do 22pF and 370pF compare to the parallel parasitic capacitance of the crystal?)
yogi wrote:On a side note, I located the Yamaha datasheet for the YM2608 (the parent of the YM2612; the same FM core). the Interesting thing I found is it's nominal Master CLK is 8MHz, so I think Sega just under-clocked it, based on the chosen system clock. So, could use a standard 8 MHz can; but it may be better to maintain compatibility with Sega VGM values?
Hm. I wonder. Page 19 of the translated OPNA datasheet shows there's a selectable clock divider of 2,3, or 6 for the FM synth, but I'm not certain what else that changes. After all, the OPNA contains its own DAC, so there's no minimum clock speed to hold a serial bitstream. Anyway, when at a divider of 6 (claimed necessary for behavior above 4MHz), the output sample clock is Mclk/144. (Much like the OPL3's is Mclk/288, or the OPL2's is Mclk/72).
Beyonds changing the necessary tuning tables, this will also slightly affect ADSR rates, the timers, and the various free-running LFOs (e.g. "AMS" and "PMS"). Not certain exactly what they're using, since their rates don't seem to be tunable.
If we can extrapolate from the OPL3, the FM LFO is fixed at Sclk÷8192, and the AM LFO is fixed at Sclk÷13440. (MESS says these magic numbers are shared with the rest of the OPLx family, but who knows if that's true for the OPNx. Apparently the OPMx family can actually control the LFOs!)
infiniteneslives wrote:I²S? or I²C? Granted I didn't look too hard, but digikey turned up a I²S DAC for $1.50, and I²C for ~$0.60.
I²S. I²C can't maintain the necessary bandwidth (at least 2+3×9=29 bittimes per sample, so 1.4Mbit/s). But let's drop this, for the other reasons you laid out.
lidnariq wrote:Then again, new old stock or working pulls of the YMF262 (OPL3) are also about the same cost as the YM3812 on ebay, and its DAC [YAC512] looks to be usually cheaper than the OPL3.
Gluing these two trains of though together, I thought I'd go ahead and compare the bitstreams we're talking about here:
YM3014 (OPL2 DAC) input format
- 16 clocks per sample (800kHz)
- falling edge of word clock marks end of word
- three idle bit periods per word (650kbit/s)
- UNsigned, LITTLE endian, µ-law-like
YMF262 (OPL3) output format
- 18 clocks per sample (1.79MHz)
- two channels interleaved per data line, two data lines, nominally quadraphonic
- two word clock lines, falling edge marks end of word
- two idle bit periods per word (3.2Mbit/s)
- UNsigned, LITTLE endian, PCM
- any number of clocks per sample, but many receivers require at least 8
- two channels interleaved per data line
- word clock toggles on bit before end of word
- Signed, BIG endian
- Many DACs annoyingly require a clock input at 256 times the sample rate.
And one even bigger tangent: Since the OPL3 doesn't really support "useful" quadraphonics (each voice can either be mixed or skipped for each output channel), I thought it would be nifty to have controllable VCFs on the DACs' outputs, and downmix that all to mono. But a digitally controlled VCF should really be done all in DSP anyway, so that's really just a pipedream.