8 IN 1 SLROM Multicartridge
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Re: 8 IN 1 SLROM Multicartridge
There is a possibility for a future version 4 in 1 for 27C040 users?
The 100 Mega Shock
Re: 8 IN 1 SLROM Multicartridge
I'm pretty certain you should be able to just take the first halves of the resultant images and have it work: the 74'174 has been wired to boot the cartridge into the first 128KiB.
You'll need to modify the menu to only offer the first four. (otherwise 5-8 will map to 1-4)
You'll need to modify the menu to only offer the first four. (otherwise 5-8 will map to 1-4)
Re: 8 IN 1 SLROM Multicartridge
There is no need for 74HC238, WRAM CE can do the job alone as a clock signal for 74HC161.
Also I have a clone MMC1 which don't have WRAM CE at all (it is NC), for this kind of MMC1 the clock signal can be generated by decoding STA $8010 with 74HC139 :
CPU R/W = 0
/ROMSEL = 0
PRG A4 = 1
Also I have a clone MMC1 which don't have WRAM CE at all (it is NC), for this kind of MMC1 the clock signal can be generated by decoding STA $8010 with 74HC139 :
CPU R/W = 0
/ROMSEL = 0
PRG A4 = 1
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Re: 8 IN 1 SLROM Multicartridge
This should work (From the first post) : Menu PatchRuslansh wrote:What a menu will work with this scheme? - download/file.php?id=1331
Yes, they also workRuslansh wrote:games using WRAM will normally work?
It should work, check everything again.Ruslansh wrote:download/file.php?id=1331 - what needs to change in the scheme that would make it work? I use w27e040 eeprom
Re: 8 IN 1 SLROM Multicartridge
хостинг картинок
Soldered this scheme. Rechecked. Menu filled from the first post. Cartridge menu starts - games does not change.
Soldered this scheme. Rechecked. Menu filled from the first post. Cartridge menu starts - games does not change.
Re: 8 IN 1 SLROM Multicartridge
Does it work with the schematic from the first post?
Re: 8 IN 1 SLROM Multicartridge
From the first post I did not. I want to do that this would work. I'll collect the cartridge MMC1 and MMC3 on the same board. I need that to one scheme worked with two mappers.
Re: 8 IN 1 SLROM Multicartridge
Check the following:Ruslansh wrote:games does not change.
* Make sure you've wired the resistor/capacitor/diode correctly. The voltage on pin 1, while the famiclone is powered and reset is pressed, should be 0V. It should then go to 5V once you release reset.
* Make sure pin 2 is connected correctly.
* Make sure pins 7, 8, 10 are grounded.
Also, try changing the capacitor to be connected to ground instead of +5V.
Re: 8 IN 1 SLROM Multicartridge
There is a menu for MMC3 mapper for games 256 kb.?
Re: 8 IN 1 SLROM Multicartridge
Farid had previously made this one for 128 KiB MMC3 games, but it could easily be modified to support 256 KiB PRG instead.
Re: 8 IN 1 SLROM Multicartridge
Ruslansh wrote: хостинг картинок
Soldered this scheme. Rechecked. Menu filled from the first post. Cartridge menu starts - games does not change.
This scheme does not work with the menu 8 in 1 but it works with the menu under MMC 3 mapper for games ninja gaiden 3 in 1
Re: 8 IN 1 SLROM Multicartridge
@Ruslansh
Posting some pictures may make me passionate
Posting some pictures may make me passionate
Re: 8 IN 1 SLROM Multicartridge
I do not understandFARID wrote:@Ruslansh
Posting some pictures may make me passionate
Re: 8 IN 1 SLROM Multicartridge
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Re: 8 IN 1 SLROM Multicartridge
I wonder how this multicart can even work. If it does, you are just lucky.
According to the schematic from your first post: If you use 74238, which has non-inverted outputs and 74174, which latches on rising edge then at the idle state - latch's CLK is 0. At the beginning of write cycle for $6000-$7fff, it goes high. At this time, the data bus does not have proper values yet (it is around 200ns after), so 74174 latches garbage.
Original MMC1 has a slight delay between begin of cycle and rising edge of WRAM+CE (70ns), but not enough.
AX5202P has even less. Nameless MMC1 clone has around 250ns (maybe that would fit), how much has KS5361 - no idea.
Two solutions:
* Do not latch data lines - latch address lines instead
OR
* Replace 74238 with 74138
According to the schematic from your first post: If you use 74238, which has non-inverted outputs and 74174, which latches on rising edge then at the idle state - latch's CLK is 0. At the beginning of write cycle for $6000-$7fff, it goes high. At this time, the data bus does not have proper values yet (it is around 200ns after), so 74174 latches garbage.
Original MMC1 has a slight delay between begin of cycle and rising edge of WRAM+CE (70ns), but not enough.
AX5202P has even less. Nameless MMC1 clone has around 250ns (maybe that would fit), how much has KS5361 - no idea.
Two solutions:
* Do not latch data lines - latch address lines instead
OR
* Replace 74238 with 74138