Ooh, I wonder if there are bus conflicts.
(checks) Yup. I bet that's why it's not working on hardware.
Ok, depending on the kind of PRG ROM you're using, there are two things to try:
1- Add an inverter (or any other gate that can serve as one) to convert R/W into /RD, and connect that to whichever of PRG ROM /OE and /CE that /ROMSEL isn't connected to
2- In the specific case of SST39 series flash, just connect /ROMSEL to PRG ROM /CE; R/W to PRG ROM /WE; and ground PRG ROM /OE. The SST39 has a funny property where it will disable the output drivers while /WE is low, but it doesn't count as a write cycle if both /WE and /OE are low. Other flash might also work this way too, but I don't know if all does.
edit:
FCEUX just tell me that the header is wrong and should be Mapper 241.
That's ... fascinating. It showed up in
fceumm rev118 with just a cryptic "fix mapper 34", and FCEUX's
explanation of what's going on in the Mapper241 implementation is actively terrible:
Code: Select all
// Mapper 7 mostly, but with SRAM or maybe prot circuit
// figure out, which games do need 5xxx area reading
static void M241Sync(void) {
setchr8(0);
setprg8r(0x10, 0x6000, 0);
if (latche & 0x80)
setprg32(0x8000, latche | 8); // no 241 actually, but why not afterall?
else
setprg32(0x8000, latche);
}
In other words ... it's BNROM, except sometimes it's not. Why not? Who knows! We don't have the hardware, so we can't say anything authoritative, and cah4e3 doesn't seem to believe in mentioning what specific thing led to a structural change like that.