Someone has asked me a question regarding the signal connections to the S-WRAM and I can't figure out the answer. I think it might be an error on the schematic but can find no evidence as such.
The question is: Why is S-CPU address bit 22 (i.e. CA22) connected to the "ENA" pin of the S-WRAM?
First, there is an underlying assumption within the question that the "ENA" pin of the S-WRAM "enables" the WRAM to function. Specifically, unless the ENA pin is asserted (i.e. logic high) then the WRAM will neither honor writes to its memory nor will it respond with (i.e. drive) valid data onto the data bus when it is read. Another way of saying this is that the ENA pin acts as another chip-select (CS) pin (of which the WRAM already has 6 others).
Second, there is another assumption that the ENA signal is active-high. This may or may not be the case, but even if it is active-low the question still needs to be answered.
The memory map for the SNES is given in Anomie's memmap.txt as follows:
Code: Select all
Banks | Addresses | Speed | Mapping
---------+-------------+-------+---------
$00-$3F | $0000-$1FFF | Slow | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
| <.......snip......> |
| $8000-$FFFF | Slow | Address Bus A + /CART
---------+-------------+-------+---------
$40-$7D | $0000-$FFFF | Slow | Address Bus A + /CART
---------+-------------+-------+---------
$7E-$7F | $0000-$FFFF | Slow | Address Bus A + /WRAM
---------+-------------+-------+---------
$80-$BF | $0000-$1FFF | Slow | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
| <.......snip......> |
| $8000-$FFFF | Note2 | Address Bus A + /CART
---------+-------------+-------+---------
$C0-$FF | $0000-$FFFF | Note2 | Address Bus A + /CART
Relating the above memory map with the assumption regarding the "ENA" pin's behavior this doesn't seem to make any sense. Specifically, if the WRAM only functions if CA22 is asserted, then that means it will only respond to read/write requests on banks $40-$7F and $C0-$FF (this covers the $7E-$7F WRAM region). But this doesn't match the above mapping because WRAM clearly does respond in banks $00-$3F and $80-$BF.
Similarly, if we say that ENA is really an active-low signal, then WRAM would only respond to read/write requests on banks $00-$3F and $80-$BF but _not_ on banks $7E-$7F.
I'm thinking one of three things is going on:
1) It's not really CA22 that's connected, it's actually some other address bit (although this would mean that multiple documents and other schematics that I've found are also wrong).
2) The assumed behavior of the "ENA" signal is totally wrong (although I can't really think of any other possible meaning for a signal with an "ENA" abbreviation)
3) I'm being an idiot and missing something painfully obvious (quite possible)
Does anyone have any insight on this?
I'd love to correct the schematic and release an update if it's a mistake.