Thanks everyone. This was very helpful. After AWJ mentioned about the 3 LSbits being only in PPU2 things made a lot more sense. I actually already knew that those bits were only in PPU2 but I wasn't connecting that with its effect on the register assignment. Cool stuff!
lidnariq wrote:By elimination, the X scroll registers have to be at least 11-bit, because when it's moved over into the fine X scroll the &4s bit isn't 0.
I just wanted to clarify on this...So you believe that all the scroll registers are 11-bit even though all the docs that I can find say they're 10-bit? It's not clear to me what purpose an 11-bit register would server. Only 10 bits are required for the maximum permissible scroll in any background configuration (I'm excluding $210D/E since those are also used for Mode 7).
From Anomie's regs.txt:
Code: Select all
x = The BG offset, at most 10 bits (some modes effectively use as few
as 8).
Note that all BGs wrap if you try to go past their edges. Thus, the
maximum offset value in BG Modes 0-6 is 1023, since you have at most 64
tiles (if x/y of BGnSC is set) of 16 pixels each (if the appropriate
bit of BGMODE is set).
I think it would be very highly unlikely for Nintendo to insert a redundant flip-flop in the circuit design. A transistor saved is a penny earned.