Oziphantom wrote:if you access the CPU regs or the Common RAM it goes at 1.8 but if you hit upper RAM or ROM it goes at 3.5 or 2.8
No.
Only the serial ports are XSlow (12 master clocks per byte, or 3 for φ1 and 9 for φ2). And you should never need to touch those unless you're using a nonstandard controller, or perhaps porting a NES game, because autopoll does it for you in the background.
All RAM in the system is Slow (φ2 = 5 master clocks), as is all ROM unless $420D is set to 1, in which case ROM in the upper half of the memory map ($8000-$FFFF in banks $80-$BF and $0000-$FFFF in banks $C0-$FF) is Fast (φ2 = 3 master clocks).
Internal CPU cycles (no bus access) and MMIO registers other than the controller ports are always Fast.
This is documented more precisely in
Anomie's SNES Memory Mapping Doc:
Code: Select all
The 'Speed' column indicates the memory access speed for that area of memory.
The SNES master clock runs at about 21MHz (probably as close to 1.89e9/88 Hz as
possible). Internal operation CPU cycles always take 6 master cycles. Fast
memory access cycles also take 6 master cycles, Slow memory access cycles take
8 master cycles, and XSlow memory access cycles take 12 master cycles.
Banks | Addresses | Speed | Mapping
---------+-------------+-------+---------
$00-$3F | $0000-$1FFF | Slow | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
| $2000-$20FF | Fast | Address Bus A
| $2100-$21FF | Fast | Address Bus B
| $2200-$3FFF | Fast | Address Bus A
| $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
| $4200-$43FF | Fast | Internal CPU registers (see Note 1 below)
| $4400-$5FFF | Fast | Address Bus A
| $6000-$7FFF | Slow | Address Bus A
| $8000-$FFFF | Slow | Address Bus A + /CART
---------+-------------+-------+---------
$40-$7D | $0000-$FFFF | Slow | Address Bus A + /CART
---------+-------------+-------+---------
$7E-$7F | $0000-$FFFF | Slow | Address Bus A + /WRAM
---------+-------------+-------+---------
$80-$BF | $0000-$1FFF | Slow | Address Bus A + /WRAM (mirror $7E:0000-$1FFF)
| $2000-$20FF | Fast | Address Bus A
| $2100-$21FF | Fast | Address Bus B
| $2200-$3FFF | Fast | Address Bus A
| $4000-$41FF | XSlow | Internal CPU registers (see Note 1 below)
| $4200-$43FF | Fast | Internal CPU registers (see Note 1 below)
| $4400-$5FFF | Fast | Address Bus A
| $6000-$7FFF | Slow | Address Bus A
| $8000-$FFFF | Note2 | Address Bus A + /CART
---------+-------------+-------+---------
$C0-$FF | $0000-$FFFF | Note2 | Address Bus A + /CART
Note 1: The address for internal CPU registers may go out Address Bus A,
however the CPU ignores the data bus. It is unknown whether the data bus
is ignored for the whole memory region, or just for those addresses which
are actually registers. It is also unknown whether CPU writes show up on
the data bus or not. Current theory is that addresses and writes will show
up, but reads may or may not, and the data bus is only ignored for those
bits of those registers actually mapped (e.g., data bus is ignored for only
bit 7 of $4211).
Note 2: If bit 0 of CPU register $420d is set, the speed is Fast, otherwise
it is Slow.