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 Post subject: Recommended FPGA boards
PostPosted: Fri Jun 09, 2017 3:30 pm 
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Hello.
First time posting on Nesdev.
I recently have been interested in learning HDL and programmable logic devices.
Is it better to start with CPLD and then move up to FPGA? Or doesn't matter?
What FPGA dev board would you guys recommend?
Thanks!


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PostPosted: Fri Jun 09, 2017 6:19 pm 
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The line between CPLD and FPGA is pretty blurred with today's programmable logic market. Traditionally a CPLD is eeprom based, and FPGA is SRAM based for the logic configuration bits. But many devices marketed as CPLDs, are actually FPGAs but the device initiallizes the SRAM itself at boot time very quickly. A good example of this is the altera Max10 CPLDs actually being cyclone FPGA cores with some initialization flash. Lattice Mach XO/XO2/XO3 "CPLDs" work this way as well.

So the definition of CPLD now is some loose definition that the developer doesn't really have to worry about initialization, and also doesn't have a extreme logic density. That said you can find devices marketed as FPGAs but they self initialize as well.


The other distinction is that devices marketed as CPLDs don't require paid licenses for the development software. But there are various FPGAs which have free licenses as well..

It's hard to suggest a specific board or device as it really depends on your goals. One of the biggest issues you wil battle is 5v signal tolerance and level shifting. There are only 1-2 devices I'm aware of that are both 5v tolerant, and still recommended for new designs. Aside from signal levels, the big questions are how many io you plan to need, and what scale of mapper you want to be able to support in the device. Here are some rules of thumb to give you a general sense of how much logic you might need for your goals.

Discrete mappers will easily fit in a 32 macrocell device.

MMC1 scale needs a 64 macrocell device as it can't really fit in 32 macrocells unless you simplify it with smaller memories or other tricks.

MMC3 scale needs ~120 macrocells.

CPLD/FPGA dev boards can be quite the challenge to use especially with high io count mappers. In some ways it can be easier to draft up your own prototype board for your targeted device.

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PostPosted: Sat Jun 10, 2017 1:54 am 
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Another difference is that devices marketted to as CPLD often contains pure programmable logic (with maybe one or two clock generators), while devices marketted as FPGA contains much more components in addition to the programmable logic, such as SRAM, multipliers, adders, and PLLs.


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PostPosted: Sat Jun 10, 2017 7:46 am 
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The devices marketed as CPLDs such as Mach XO2/XO3 and altera max10 have those FPGA components. That statement really applied to true CPLDs, not all devices marketed as a CPLD.

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PostPosted: Sat Jun 10, 2017 9:46 pm 
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Thanks guys for the detailed explanation.
I'm doing some more reading and research before I commit to a board.
I think I might get a simple/cheap cpld just to make some blinking light basic tutorials.

Just out of curiosity, how many macrocells would be needed to recreate a RC2A03, the PPU or an entire NES?
Thanks!


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PostPosted: Sat Jun 10, 2017 11:00 pm 
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It's also possible to get some familiarity with FPGAs or CPLDs just by using the simulators included with the software kits. You just need to add a little more into your Verilog (no idea about VHDL but I'm sure it's similar) to set up values into the inputs, then you can view the outputs and see if things work as you expect. This is doable with Quartus, Diamond, or ISE, all free versions. Usually you have to jump through a few hoops/registration to install and get the free license, but you'll be doing that anyways when you start using a board.


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PostPosted: Sun Jun 11, 2017 1:33 am 
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infiniteneslives wrote:
The devices marketed as CPLDs such as Mach XO2/XO3 and altera max10 have those FPGA components. That statement really applied to true CPLDs, not all devices marketed as a CPLD.

So how do you know when you bought a CPLD marketted to as a FPGA or a FPGA marketted as a CPLD ?


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PostPosted: Sun Jun 11, 2017 4:16 am 
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Be advised that CPLDs have non-volatile memory so when programmed, they store the circuit description until next reprogram. In contrary, FPGAs will need some kind of external non-volatile memory because their internal memory content's will vanish after power down.

Also, CPLDs have limit of reprogramming cycles (XC95xx -> 10000, EP2K240 -> 100), while FPGAs don't.


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PostPosted: Sun Jun 11, 2017 2:58 pm 
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Bregalad wrote:
infiniteneslives wrote:
The devices marketed as CPLDs such as Mach XO2/XO3 and altera max10 have those FPGA components. That statement really applied to true CPLDs, not all devices marketed as a CPLD.

So how do you know when you bought a CPLD marketted to as a FPGA or a FPGA marketted as a CPLD ?


I think the main reason an FPGA would be marketed as a CPLD is because apparently to a lot of people (as a google search would show), the defining characteristic of an FPGA is that the configuration is stored externally. So it could be a way of simply letting people know that hey, this exists. The previous MAX series were CPLDs. If you look at the actual datasheet for MachXO2 (and probably MAX10 too), the term CPLD is nowhere in it. They are definitely non-volatile FPGAs. So as usual, it's best to just ignore the marketing and go straight to the actual technical specs. :)

It seems that true CPLDs are pretty much a dead-end technology at this point. Maybe there is some architectural difference, I've seen it said that CPLDs have more predictable timing. But for all I know that could be because people are comparing tiny CPLDs to large FPGAs, so the signals would have to be sort of further removed from the I/O pins.


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PostPosted: Mon Jun 26, 2017 11:31 am 
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I've been wanting to slap an FPGA onto a custom board for an NES cart project for a while now, though I still have many skill gaps to overcome.

I've had the internal dialog about CPLD vs FPGA as part of my though process. One concern I had is will an FPGA load it's configuration bits fast enough to be work properly, and if there's some timing requirement needed if say... you had all your cart pins wired to FPGA I/O pins. Can the system handle waiting for an FPGA to initialize? If all the outputs are floating will the system wait for them to have valid signals and such?


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PostPosted: Mon Jun 26, 2017 11:37 am 
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The Drip mapper has pull-ups on the upper PRG ROM address lines so that code in the fixed bank can wait in a loop for the FPGA to load its configuration.


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PostPosted: Mon Jun 26, 2017 11:47 am 
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tepples wrote:
The Drip mapper has pull-ups on the upper PRG ROM address lines so that code in the fixed bank can wait in a loop for the FPGA to load its configuration.

Many (most?) FPGAs have internal pullups on every I/O line before and during configuration time.


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PostPosted: Mon Jun 26, 2017 11:47 am 
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The iCE40 FPGAs go from cold to "load contents out of SPI ROM" and operational in about 1ms... to the best of my memory, that should be consistently faster than the CIC releases /RESET.


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PostPosted: Mon Jun 26, 2017 4:47 pm 
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I wouldn't recommend selecting an FPGA that doesn't initialize itself for your first project. There are decent number of self initialing small FPGAs which should initialize themselves with more than enough time. That also includes devices which are marketed as CPLDs, but are techically self initializing FPGAs.

Issues such as 5v tolerance/level shifting, io count, logic cell count, pcb routing/soldering ease, will be the bigger factors/considerations that will push you into CPLD or FPGA.

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