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PostPosted: Fri Dec 15, 2017 1:09 pm 
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The SST39 flash parts also use a 15-bit address key (instead of 12 bit)


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PostPosted: Fri Dec 15, 2017 1:48 pm 
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... /CS (/MREQ) decodes $A000-$FDFF ?

Why did they do that?


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PostPosted: Fri Dec 15, 2017 2:13 pm 
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It could have decoded the whole $8000-$FFFF half of the memory map, but...
$8000-$9FFF is VRAM, which is on a separate external bus.
$FE00-$FEFF is OAM, which is on a separate internal bus.
$FF00-$FFFF is IO and HRAM, which is also on a separate internal bus.

So that range is what's left when other things have poked holes in the top half of the memory map. Hardware-wise, the DMG is using an SRAM chip with two CE lines, one active low and one active high. /CS=/CE1 and A14=CE2. And that /CS is physically the same signal as is routed to the cart slot. And that's how echo RAM happens too.

Which reminds me... Iirc, some EMS cart have a bus conflict between echo RAM and SRAM. Which suggests their address decoding is a lazy RAM_CS=CS or A13. Ie, they're ignoring the state of A14.

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PostPosted: Fri Dec 15, 2017 2:21 pm 
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So you said that detecting when both /MREQ and A14 are low should safely detect the region? There are latches that have an active low enable (such as used in the NES, i.e. 74'377 and 74'161) that could decode $A000-$BFFF without needing extra hardware, then. They couldn't distinguish between reads and writes, but there shouldn't be any accidental reads/writes to the region anyway... right?


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PostPosted: Fri Dec 15, 2017 3:42 pm 
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lidnariq wrote:
So you said that detecting when both /MREQ and A14 are low should safely detect the region? There are latches that have an active low enable (such as used in the NES, i.e. 74'377 and 74'161) that could decode $A000-$BFFF without needing extra hardware, then. They couldn't distinguish between reads and writes, but there shouldn't be any accidental reads/writes to the region anyway... right?
What are you aiming for? A really dirty one chip solution? Keep in mind that unless you did the extra logic for handling the decoding for bank 0 (requiring 1-2 74' AND chips or similar) the hardware would be non-trivially incompatible with most software because it would switch out 32 kB at a time instead of the usual 16 kB banks.

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PostPosted: Fri Dec 15, 2017 4:17 pm 
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nitro2k01 wrote:
What are you aiming for?
This is good enough reason by itself:
nitro2k01 wrote:
Actually, it WOULD be a problem for one chip I've seen in the wild: AM29F016 (as opposed to AM29F016b or some other variant of the chip.) Not because it was lacking the multi-write sequence, but because the addresses used for it needed all of A0-A14 to be a checkerboard pattern. Literally $2AAA and $5555. In this case, filtering writes would make sense.
The SST39 parts are currently the cheapest option for 5V flash smaller than 1MiB.

Splitting the memory region for differing read and write regions of flash is more logically complex than just moving the bankswitching register out of the same region.

I wasn't actually considering a board with 32K banking, although I have to admit that one 74HC161 and one SST39SF040 would certainly be the sweet spot for storage + cost. The '161 can even guarantee that the first bank is selected when it turns on, because it has the asynchronous reset input (that could be tied to the /RST signal on the cart slot)


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PostPosted: Sat Dec 16, 2017 4:11 am 
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(Maybe) unrelated to the flash discussion, but BennVenn said something about why worse FRAM boards failed to save on GBA SP. The FRAM required a CS pulse before each write, which older Gameboys did but the SP did not, and so he had to work around it in the CPLD.


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PostPosted: Tue Jul 24, 2018 2:56 pm 
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I can help out with a board layout for Game Boy games with up to 256 kb. If somebody needs it, please send me a pm or a message via the contact form on my website https://the-green-screen.com.


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