Compiling Verilog into SW Emulators

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defparam
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Joined: Sat Oct 04, 2014 3:48 pm

Compiling Verilog into SW Emulators

Post by defparam » Wed Apr 04, 2018 6:23 pm

Hi All!

With FPGA consoles and new SD2SNES co-processor cores being all the rage these days I feel like verilog and retro FPGA HW development is starting to heat up. For those interested in playing around with verilog I created a neat example of compiling a verilog model into C++ (using Verilator) and then linking the C++ into higan (more info described in the repo).

Here is my demo: https://www.youtube.com/watch?v=T88LhuoQ7pg
Here is the source code: https://github.com/defparam/higan-verilog

I was thinking about taking a similar example and porting Redguyyy's GSU verilog implementation into higan to see how well it would work or to compare inputs/outputs against byuu's GSU sw emulation core and try to find hidden bugs. Anyway, if anyone is interested in this co-simulation stuff take a peek!

Best,
defparam

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thefox
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Location: Tampere, Finland
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Re: Compiling Verilog into SW Emulators

Post by thefox » Thu Apr 05, 2018 12:47 am

Nice to see a proof of concept about this :)
Download STREEMERZ for NES from fauxgame.com! — Some other stuff I've done: fo.aspekt.fi

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