Timing properties of the 2A03's write cycles

Discuss hardware-related topics, such as development cartridges, CopyNES, PowerPak, EPROMs, or whatever.

Moderators: B00daW, Moderators

Post Reply
lidnariq
Posts: 10432
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Timing properties of the 2A03's write cycles

Post by lidnariq » Sun Nov 17, 2019 9:12 pm

I figured I wanted this data, so I just took a very simple program (an endless stream of STX z:0 when X=$FF, plus a tiny bit of support code) and measured relative timings.

This is on a 60MHz 1GS/s 'scope, so high frequency components are attenuated out and the exact timing is somewhat dubious ... but not that dubious. (In practice, this appears to be a 1st-order lowpass at 60MHz, so a perfectly sharp edge should transition 63% (1-1/e) of the way in roughly 1/60MHz ≈ 17ns)

M2 falls 60-56ns before R/W does. M2 rises 70-90ns after R/W does. A rising edge of R/W is slower (~20ns) than a falling edge (~10ns) or either edge of M2 (~5ns).

When executing STX z:0, D0 is pulled up by the 2A03 approximately 250-260ns after R/W falls, rising to about 4V. This is also about 100ns after M2 has risen, and roughly 90 after /ROMSEL would have fallen. (It's 660ns after the previous time /ROMSEL fell, and 460ns before the next time it does.) Propagation delay through the 74'139 on my NES-CPU-07 is about 20ns. Propagation delay through the 74'139 for NEs-internal WRAM (and thus presumably also the PPU) is about 30ns. (I assume it's faster than 2x20 due to less capacitance).

If the CPU exported φ2 instead of M2, even if only during write cycles, this would be fine: φ1 would be 280ns long, and the data bus would be stable roughly 20ns before φ2 was asserted.

I haven't tested DMA timing, but it's probably better. Unfortunately, it will be harder to test because the sprite DMA will always leave the same value on the external data bus that the 2A03 will drive in the following cycle.

So it seems that when the CPU writes to the PPU or any other peripheral, the wrong value is always on the data bus for a whole half dot. The surprising part is that everything isn't glitchy.

krzysiobal
Posts: 838
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Re: Timing properties of the 2A03's write cycles

Post by krzysiobal » Mon Nov 18, 2019 12:37 am

So it seems that when the CPU writes to the PPU or any other peripheral, the wrong value is always on the data bus for a whole half dot. The surprising part is that everything isn't glitchy.
That's why during write cycle all memory chips (RAM, ROM) latches internally the destination address on the falling edge of its /CE chip and data value on the rising one.
Same goes for mapper chips that use only data bus (like UNROM's 74161).

plainsteve
Posts: 28
Joined: Tue Jan 23, 2018 11:19 pm

Re: Timing properties of the 2A03's write cycles

Post by plainsteve » Mon Nov 18, 2019 10:51 am

Thanks for doing this and posting! I think it will help me with issues I brought up in this thread:

viewtopic.php?f=9&t=19004

nocash
Posts: 1341
Joined: Fri Feb 24, 2012 12:09 pm
Contact:

Re: Timing properties of the 2A03's write cycles

Post by nocash » Mon Nov 18, 2019 4:44 pm

lidnariq wrote:M2 falls 60-56ns before R/W does. M2 rises 70-90ns after R/W does. A rising edge of R/W is slower (~20ns) than a falling edge (~10ns) or either edge of M2 (~5ns) ...
A drawing or annotated photo/screenshot might be clearer : )

Wrong data for a half cycle may be like what krzysiobal has said. But is that specific to writes, or also same for reads?

Btw. I was wondering if read and write timings differ. For the SNES, you mentioned somewhere that the low:high ratio on sysclk pin differs for normal (read?) access and dma access. My guess would be that read and write might each have different ratios (optimized for faster cpu-side vs slower memory-side), and dma having yet another medium ratio (because it does both read and write memory at once).
homepage - patreon - you can think of a bit as a bottle that is either half full or half empty

lidnariq
Posts: 10432
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Timing properties of the 2A03's write cycles

Post by lidnariq » Mon Nov 18, 2019 6:12 pm

nocash wrote:A drawing or annotated photo/screenshot might be clearer : )
Good point. If I'd made one I probably would have noticed things I failed to measure... but the above is as follows:

This would have been a lot easier if my 'scope had 4 channels instead of 2.

Code: Select all

 (10ns) 0  40  80 120 160 200 240 280 320 360 400 440 480 520 560 600
   phi0 \___________________________/^^^^^^^^^^^^^^^^^^^^^^^^^^^\____ (assumed)
     M2 \____________________/^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\____
/ROMSEL __/^^^^^^^^^^^^^^^^^^^^\__________________________________/^^ (when relevant)
    R/W ^^^^^\_______________________________________________________ (read to write cycle)
     D0 ???????ZZZZZZZZZZZZZZZZZZZZZZZZ^^^^^^^^^^^^^^^^^^^^^^^^^^^^??
    R/W ____________/^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (write to read cycle)
Things I have not measured: when does the 2A03 stop driving the data bus? How does the address bus timing compare?

Rockwells's 6502 datahseet says that for their 2MHz parts:
Time from phi2 fall to address and R/W stable: max 140ns (compare 60ns measured above)
Time from phi2 rise to data bus stable during write: max 100ns (compare 30ns measured above)
But is that specific to writes
Specific to writes. This is about, during a write cycle, how long it takes the 2A03 (6502?) to get data from the core to the outside world.
or also same for reads?
Read timing is different anyway; in that case the CPU is telling the outside world "hey, I'd like something else to drive data on the data bus", and ideally M2 would go high as soon as the address bus (and R/W) were stable. In contrast, writes additionally depend on the data bus being stable.
BTW, I was wondering if read and write timings differ.
No. For the 2A03G, we know there's two ÷12 twisted ring counters (one on falling edges, one on rising edges); one stage comes out directly serving as phi0 to the internal 6502, and that stage is ORed with another from the other counter to make M2. Hence the 5/8 (or pedantically 15/24) duty.

Interestingly, Rockwell's 6502 datasheet insinuates (but doesn't characterize) a delay from phi0 to phi2, so that may additionally complicate things.

The decapped image of the original 2A03 still has this same structure, so there we know that the duty cycle can't be 3/4 (as has been said), but must instead be 17/24 or 19/24 instead. (However, I don't know of anyone having re-measured this since the decapped image showed up). Additionally, we don't know anything about the M2 duty cycle of the 2A07 or the UA6527P.
For the SNES, you mentioned somewhere that the low:high ratio on sysclk pin differs for normal (read?) access and dma access.
Right. We know that DMA access is 4:4, "slow" access is 3:5, and "fast" access is 3:3. We don't know the timing for "very slow" but I suspect it's 3:9.
My guess would be that read and write might each have different ratios (optimized for faster cpu-side vs slower memory-side),
Indeed, that would have been clever, but sadly it doesn't seem to be true.

Post Reply