Sunsoft 3 testing

Discuss hardware-related topics, such as development cartridges, CopyNES, PowerPak, EPROMs, or whatever.

Moderators: B00daW, Moderators

Post Reply
krzysiobal
Posts: 636
Joined: Sun Jun 12, 2011 12:06 pm
Location: Poland

Sunsoft 3 testing

Post by krzysiobal » Thu Feb 13, 2020 8:46 am

Looks like there is no pinout nor description of chip, so high time to crush the piggy bank and buy patient for testing.

Code: Select all

                 .---\/---.
       +RESET -> | 01  42 | -- VCC                
 (n)       M2 -> | 02  41 | <- EXT /IRQ (n/c)
 (nr) CPU A11 -> | 03  40 | <- CPU D7  (nr)        
 (nr) CPU A12 -> | 04  39 | <- CPU D6  (nr)        
 (nr) CPU A13 -> | 05  38 | <- CPU D5  (nr)        
 (n)  CPU A14 -> | 06  37 | <- CPU D4  (nr)        
 (n)  /ROMSEL -> | 07  36 | <- CPU D3  (nr)        
 (n)  CPU R/W -> | 08  35 | <- CPU D2  (nr)        
 (r)  PRG /CE <- | 09  34 | <- CPU D1  (nr)        
 (n)  CIR A10 <- | 10  33 | <- CPU D0  (nr)            
 (r)  CHR /CE <- | 11  32 | -> /RAM-CE (n/c)
 (nr) PPU A10 <- | 12  31 | -> RAM+CE  (n/c)
 (n)  PPU A11 -> | 13  30 | <- PPU A13 (n)       
 (n)  PPU A12 -> | 14  29 | <- PPU /RD (n)          
 (r)  CHR A16 <- | 15  28 | -> /IRQ    (n)    
 (r)  CHR A15 <- | 16  27 | -> PRG A14 (r) 
 (r)  CHR A14 <- | 17  26 | -> PRG A15 (r) 
 (r)  CHR A13 <- | 18  25 | -> PRG A16 (r) 
 (r)  CHR A12 <- | 19  24 | -> PRG A17 (n/c) 
 (r)  CHR A11 <- | 20  23 | -> /PRG A17 (n/c)      
      GND     -- | 21  22 | -> $f800.4 (n/c)
                 `--------'
                  SUNSOFT-3
                  
[...XPPPP} at $f800


Notes:
* Mapper 067
* Pins marked as n/c were not connected in subject cartridge [Fantasy Zone II (J)].
* Pin 1 connected to the following M2-based reset detector. However, even if M2 stops toggling, PRG/CHR banks still can be changed, and nothing is held in reset. Maybe it is just used to initalize some internals of the chip.

Code: Select all

   M2-+-|<---+--pin1
      |      |
      +--1k--+
             |
            82p
             |
            GND
* Pin 22 reflects the value of $f800.4, no matter what address CPU is reading
* Purpose of pin 23 is probably to allow two 128k PRG-ROMS to be connected. If they have /CE+/OE then PRG1/CE=PRG2/CE=PRG/CE, PRG1/OE=PRG A17, PRG2/OE=/PRG A17. If they have single /CE then using external OR gate PRG1/CE = PRG/CE || PRG A17, PRG2/CE = PRG/CE || /PRG A17
* Pins 31/32 are active for $6000-$7fff
* Writing to $c800 or $d800 does NOT cause IRQ to be acked. Instead, writing to any of those registers ACKS:
$8000, $9000, $a000, $b000, $c000, $d000, $e000, $f000 (looking at the IRQ handler in Fantasy Zone 2 it indeed writes to $8000 to ack)
* Pin 41 is input, internally pulled-up to +5V. I don't quite know how it works, but when tied to GND (witk 1k resistor for safety), the game does not boot. After more testing it looks like it is responsible for some kind of external interupt? Here are my testing scenarios:
1) $d800.4=1 and this pin goes to GND, /IRQ is immediatelly triggered and cannot be acked in any way. The only way is to disconnect pin 41 from GND and then write to $x000 (x=$8..f$)
2) if $d800.4=0 and this pin goes to GND, IRQ is not asserted. Setting $d800.4 to 1 immediatelly triggers /IRQ and it cannot be acked in any way. The only way is to disconnect pin 41 from GND and then write to $x000 (x=$8..f$)

Maybe along with pin 22, it can be used to communnicate with some external chip that can also assert interrupts (additional audio chip?)

lidnariq
Posts: 9008
Joined: Sun Apr 13, 2008 11:12 am
Location: Seattle

Re: Sunsoft 3 testing

Post by lidnariq » Tue Feb 18, 2020 12:12 am

krzysiobal wrote:
Thu Feb 13, 2020 8:46 am
* Pin 1 connected to the following M2-based reset detector. However, even if M2 stops toggling, PRG/CHR banks still can be changed, and nothing is held in reset. Maybe it is just used to initalize some internals of the chip.

Code: Select all

   M2-+-|<---+--pin1
      |      |
      +--1k--+
             |
            82p
             |
            GND
It's too fast to be a reset detector. 1 kΩ × 82 pF = 82 ns. Also, M2 goes Hi-Z during reset, not high. So this has to be something that's for asymmetrically delaying M2: falling edges should coincide, but rising edges are delayed by roughly 82ns.

Maybe the internal registers are transparent latches instead of clocked, and this pulse shaping means that the signal received on pin 1 will indicate that the data bus is valid during the entire write? Pin 2, M2, might only be used for the IRQ.

The Vs. Platoon board ("2UNI-E05" per one archived eBay auction, but I think the pictures on John's Arcade and Playchoice.Riemenschnieder are probably "-E04") has a 74LS04 and no obvious diode, so it has to work there despite the 2A03's 17/24 or 19/24 M2 duty cycle. It's conceivable that R1 (1kΩ) and C3 (unknown, small, green, ceramic) somehow serve as the same pulse shaper there.

Post Reply